1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) { 28 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant); 29 StringRef Mnemonic(AsmString); 30 // Extract a mnemonic assuming it's separated by \t 31 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; }); 32 33 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic. 34 // Replace it with "CC" in-place. 35 size_t CondPos = Mnemonic.find("${cond}"); 36 if (CondPos != StringRef::npos) 37 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC"); 38 return Mnemonic.upper(); 39 } 40 41 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 42 /// Useful for switch statements and the like. 43 /// 44 /// @param init - A reference to the BitsInit to be decoded. 45 /// @return - The field, with the first bit in the BitsInit as the lowest 46 /// order bit. 47 static uint8_t byteFromBitsInit(BitsInit &init) { 48 int width = init.getNumBits(); 49 50 assert(width <= 8 && "Field is too large for uint8_t!"); 51 52 int index; 53 uint8_t mask = 0x01; 54 55 uint8_t ret = 0; 56 57 for (index = 0; index < width; index++) { 58 if (cast<BitInit>(init.getBit(index))->getValue()) 59 ret |= mask; 60 61 mask <<= 1; 62 } 63 64 return ret; 65 } 66 67 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 68 /// name of the field. 69 /// 70 /// @param rec - The record from which to extract the value. 71 /// @param name - The name of the field in the record. 72 /// @return - The field, as translated by byteFromBitsInit(). 73 static uint8_t byteFromRec(const Record* rec, StringRef name) { 74 BitsInit* bits = rec->getValueAsBitsInit(name); 75 return byteFromBitsInit(*bits); 76 } 77 78 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 79 const CodeGenInstruction &insn, 80 InstrUID uid) { 81 UID = uid; 82 83 Rec = insn.TheDef; 84 Name = std::string(Rec->getName()); 85 Spec = &tables.specForUID(UID); 86 87 if (!Rec->isSubClassOf("X86Inst")) { 88 ShouldBeEmitted = false; 89 return; 90 } 91 92 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 93 OpMap = byteFromRec(Rec, "OpMapBits"); 94 Opcode = byteFromRec(Rec, "Opcode"); 95 Form = byteFromRec(Rec, "FormBits"); 96 Encoding = byteFromRec(Rec, "OpEncBits"); 97 98 OpSize = byteFromRec(Rec, "OpSizeBits"); 99 AdSize = byteFromRec(Rec, "AdSizeBits"); 100 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 101 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 102 HasVEX_W = Rec->getValueAsBit("HasVEX_W"); 103 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W"); 104 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 105 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 106 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 107 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 108 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 109 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 110 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 111 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 112 113 Name = std::string(Rec->getName()); 114 115 Operands = &insn.Operands.OperandList; 116 117 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 118 119 EncodeRC = HasEVEX_B && 120 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 121 122 // Check for 64-bit inst which does not require REX 123 Is32Bit = false; 124 Is64Bit = false; 125 // FIXME: Is there some better way to check for In64BitMode? 126 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 127 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 128 if (Predicates[i]->getName().contains("Not64Bit") || 129 Predicates[i]->getName().contains("In32Bit")) { 130 Is32Bit = true; 131 break; 132 } 133 if (Predicates[i]->getName().contains("In64Bit")) { 134 Is64Bit = true; 135 break; 136 } 137 } 138 139 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 140 ShouldBeEmitted = false; 141 return; 142 } 143 144 ShouldBeEmitted = true; 145 } 146 147 void RecognizableInstr::processInstr(DisassemblerTables &tables, 148 const CodeGenInstruction &insn, 149 InstrUID uid) 150 { 151 // Ignore "asm parser only" instructions. 152 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 153 return; 154 155 RecognizableInstr recogInstr(tables, insn, uid); 156 157 if (recogInstr.shouldBeEmitted()) { 158 recogInstr.emitInstructionSpecifier(); 159 recogInstr.emitDecodePath(tables); 160 } 161 } 162 163 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 164 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 165 (HasEVEX_KZ ? n##_KZ : \ 166 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 167 168 InstructionContext RecognizableInstr::insnContext() const { 169 InstructionContext insnContext; 170 171 if (Encoding == X86Local::EVEX) { 172 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 173 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 174 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 175 } 176 // VEX_L & VEX_W 177 if (!EncodeRC && HasVEX_LPrefix && HasVEX_W) { 178 if (OpPrefix == X86Local::PD) 179 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 180 else if (OpPrefix == X86Local::XS) 181 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 182 else if (OpPrefix == X86Local::XD) 183 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 184 else if (OpPrefix == X86Local::PS) 185 insnContext = EVEX_KB(IC_EVEX_L_W); 186 else { 187 errs() << "Instruction does not use a prefix: " << Name << "\n"; 188 llvm_unreachable("Invalid prefix"); 189 } 190 } else if (!EncodeRC && HasVEX_LPrefix) { 191 // VEX_L 192 if (OpPrefix == X86Local::PD) 193 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 194 else if (OpPrefix == X86Local::XS) 195 insnContext = EVEX_KB(IC_EVEX_L_XS); 196 else if (OpPrefix == X86Local::XD) 197 insnContext = EVEX_KB(IC_EVEX_L_XD); 198 else if (OpPrefix == X86Local::PS) 199 insnContext = EVEX_KB(IC_EVEX_L); 200 else { 201 errs() << "Instruction does not use a prefix: " << Name << "\n"; 202 llvm_unreachable("Invalid prefix"); 203 } 204 } else if (!EncodeRC && HasEVEX_L2Prefix && HasVEX_W) { 205 // EVEX_L2 & VEX_W 206 if (OpPrefix == X86Local::PD) 207 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 208 else if (OpPrefix == X86Local::XS) 209 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 210 else if (OpPrefix == X86Local::XD) 211 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 212 else if (OpPrefix == X86Local::PS) 213 insnContext = EVEX_KB(IC_EVEX_L2_W); 214 else { 215 errs() << "Instruction does not use a prefix: " << Name << "\n"; 216 llvm_unreachable("Invalid prefix"); 217 } 218 } else if (!EncodeRC && HasEVEX_L2Prefix) { 219 // EVEX_L2 220 if (OpPrefix == X86Local::PD) 221 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 222 else if (OpPrefix == X86Local::XD) 223 insnContext = EVEX_KB(IC_EVEX_L2_XD); 224 else if (OpPrefix == X86Local::XS) 225 insnContext = EVEX_KB(IC_EVEX_L2_XS); 226 else if (OpPrefix == X86Local::PS) 227 insnContext = EVEX_KB(IC_EVEX_L2); 228 else { 229 errs() << "Instruction does not use a prefix: " << Name << "\n"; 230 llvm_unreachable("Invalid prefix"); 231 } 232 } 233 else if (HasVEX_W) { 234 // VEX_W 235 if (OpPrefix == X86Local::PD) 236 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 237 else if (OpPrefix == X86Local::XS) 238 insnContext = EVEX_KB(IC_EVEX_W_XS); 239 else if (OpPrefix == X86Local::XD) 240 insnContext = EVEX_KB(IC_EVEX_W_XD); 241 else if (OpPrefix == X86Local::PS) 242 insnContext = EVEX_KB(IC_EVEX_W); 243 else { 244 errs() << "Instruction does not use a prefix: " << Name << "\n"; 245 llvm_unreachable("Invalid prefix"); 246 } 247 } 248 // No L, no W 249 else if (OpPrefix == X86Local::PD) 250 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 251 else if (OpPrefix == X86Local::XD) 252 insnContext = EVEX_KB(IC_EVEX_XD); 253 else if (OpPrefix == X86Local::XS) 254 insnContext = EVEX_KB(IC_EVEX_XS); 255 else if (OpPrefix == X86Local::PS) 256 insnContext = EVEX_KB(IC_EVEX); 257 else { 258 errs() << "Instruction does not use a prefix: " << Name << "\n"; 259 llvm_unreachable("Invalid prefix"); 260 } 261 /// eof EVEX 262 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 263 if (HasVEX_LPrefix && HasVEX_W) { 264 if (OpPrefix == X86Local::PD) 265 insnContext = IC_VEX_L_W_OPSIZE; 266 else if (OpPrefix == X86Local::XS) 267 insnContext = IC_VEX_L_W_XS; 268 else if (OpPrefix == X86Local::XD) 269 insnContext = IC_VEX_L_W_XD; 270 else if (OpPrefix == X86Local::PS) 271 insnContext = IC_VEX_L_W; 272 else { 273 errs() << "Instruction does not use a prefix: " << Name << "\n"; 274 llvm_unreachable("Invalid prefix"); 275 } 276 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 277 insnContext = IC_VEX_L_OPSIZE; 278 else if (OpPrefix == X86Local::PD && HasVEX_W) 279 insnContext = IC_VEX_W_OPSIZE; 280 else if (OpPrefix == X86Local::PD && Is64Bit && 281 AdSize == X86Local::AdSize32) 282 insnContext = IC_64BIT_VEX_OPSIZE_ADSIZE; 283 else if (OpPrefix == X86Local::PD && Is64Bit) 284 insnContext = IC_64BIT_VEX_OPSIZE; 285 else if (OpPrefix == X86Local::PD) 286 insnContext = IC_VEX_OPSIZE; 287 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 288 insnContext = IC_VEX_L_XS; 289 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 290 insnContext = IC_VEX_L_XD; 291 else if (HasVEX_W && OpPrefix == X86Local::XS) 292 insnContext = IC_VEX_W_XS; 293 else if (HasVEX_W && OpPrefix == X86Local::XD) 294 insnContext = IC_VEX_W_XD; 295 else if (HasVEX_W && OpPrefix == X86Local::PS) 296 insnContext = IC_VEX_W; 297 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 298 insnContext = IC_VEX_L; 299 else if (OpPrefix == X86Local::XD) 300 insnContext = IC_VEX_XD; 301 else if (OpPrefix == X86Local::XS) 302 insnContext = IC_VEX_XS; 303 else if (OpPrefix == X86Local::PS) 304 insnContext = IC_VEX; 305 else { 306 errs() << "Instruction does not use a prefix: " << Name << "\n"; 307 llvm_unreachable("Invalid prefix"); 308 } 309 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 310 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 311 insnContext = IC_64BIT_REXW_OPSIZE; 312 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 313 insnContext = IC_64BIT_REXW_ADSIZE; 314 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 315 insnContext = IC_64BIT_XD_OPSIZE; 316 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 317 insnContext = IC_64BIT_XS_OPSIZE; 318 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 319 insnContext = IC_64BIT_OPSIZE_ADSIZE; 320 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 321 insnContext = IC_64BIT_OPSIZE_ADSIZE; 322 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 323 insnContext = IC_64BIT_OPSIZE; 324 else if (AdSize == X86Local::AdSize32) 325 insnContext = IC_64BIT_ADSIZE; 326 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 327 insnContext = IC_64BIT_REXW_XS; 328 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 329 insnContext = IC_64BIT_REXW_XD; 330 else if (OpPrefix == X86Local::XD) 331 insnContext = IC_64BIT_XD; 332 else if (OpPrefix == X86Local::XS) 333 insnContext = IC_64BIT_XS; 334 else if (HasREX_WPrefix) 335 insnContext = IC_64BIT_REXW; 336 else 337 insnContext = IC_64BIT; 338 } else { 339 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 340 insnContext = IC_XD_OPSIZE; 341 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 342 insnContext = IC_XS_OPSIZE; 343 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 344 insnContext = IC_XD_ADSIZE; 345 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 346 insnContext = IC_XS_ADSIZE; 347 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 348 insnContext = IC_OPSIZE_ADSIZE; 349 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 350 insnContext = IC_OPSIZE_ADSIZE; 351 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 352 insnContext = IC_OPSIZE; 353 else if (AdSize == X86Local::AdSize16) 354 insnContext = IC_ADSIZE; 355 else if (OpPrefix == X86Local::XD) 356 insnContext = IC_XD; 357 else if (OpPrefix == X86Local::XS) 358 insnContext = IC_XS; 359 else 360 insnContext = IC; 361 } 362 363 return insnContext; 364 } 365 366 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 367 // The scaling factor for AVX512 compressed displacement encoding is an 368 // instruction attribute. Adjust the ModRM encoding type to include the 369 // scale for compressed displacement. 370 if ((encoding != ENCODING_RM && 371 encoding != ENCODING_VSIB && 372 encoding != ENCODING_SIB) ||CD8_Scale == 0) 373 return; 374 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 375 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 376 (encoding == ENCODING_SIB) || 377 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 378 "Invalid CDisp scaling"); 379 } 380 381 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 382 unsigned &physicalOperandIndex, 383 unsigned numPhysicalOperands, 384 const unsigned *operandMapping, 385 OperandEncoding (*encodingFromString) 386 (const std::string&, 387 uint8_t OpSize)) { 388 if (optional) { 389 if (physicalOperandIndex >= numPhysicalOperands) 390 return; 391 } else { 392 assert(physicalOperandIndex < numPhysicalOperands); 393 } 394 395 while (operandMapping[operandIndex] != operandIndex) { 396 Spec->operands[operandIndex].encoding = ENCODING_DUP; 397 Spec->operands[operandIndex].type = 398 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 399 ++operandIndex; 400 } 401 402 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 403 404 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 405 // Adjust the encoding type for an operand based on the instruction. 406 adjustOperandEncoding(encoding); 407 Spec->operands[operandIndex].encoding = encoding; 408 Spec->operands[operandIndex].type = 409 typeFromString(std::string(typeName), HasREX_WPrefix, OpSize); 410 411 ++operandIndex; 412 ++physicalOperandIndex; 413 } 414 415 void RecognizableInstr::emitInstructionSpecifier() { 416 Spec->name = Name; 417 418 Spec->insnContext = insnContext(); 419 420 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 421 422 unsigned numOperands = OperandList.size(); 423 unsigned numPhysicalOperands = 0; 424 425 // operandMapping maps from operands in OperandList to their originals. 426 // If operandMapping[i] != i, then the entry is a duplicate. 427 unsigned operandMapping[X86_MAX_OPERANDS]; 428 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 429 430 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 431 if (!OperandList[operandIndex].Constraints.empty()) { 432 const CGIOperandList::ConstraintInfo &Constraint = 433 OperandList[operandIndex].Constraints[0]; 434 if (Constraint.isTied()) { 435 operandMapping[operandIndex] = operandIndex; 436 operandMapping[Constraint.getTiedOperand()] = operandIndex; 437 } else { 438 ++numPhysicalOperands; 439 operandMapping[operandIndex] = operandIndex; 440 } 441 } else { 442 ++numPhysicalOperands; 443 operandMapping[operandIndex] = operandIndex; 444 } 445 } 446 447 #define HANDLE_OPERAND(class) \ 448 handleOperand(false, \ 449 operandIndex, \ 450 physicalOperandIndex, \ 451 numPhysicalOperands, \ 452 operandMapping, \ 453 class##EncodingFromString); 454 455 #define HANDLE_OPTIONAL(class) \ 456 handleOperand(true, \ 457 operandIndex, \ 458 physicalOperandIndex, \ 459 numPhysicalOperands, \ 460 operandMapping, \ 461 class##EncodingFromString); 462 463 // operandIndex should always be < numOperands 464 unsigned operandIndex = 0; 465 // physicalOperandIndex should always be < numPhysicalOperands 466 unsigned physicalOperandIndex = 0; 467 468 #ifndef NDEBUG 469 // Given the set of prefix bits, how many additional operands does the 470 // instruction have? 471 unsigned additionalOperands = 0; 472 if (HasVEX_4V) 473 ++additionalOperands; 474 if (HasEVEX_K) 475 ++additionalOperands; 476 #endif 477 478 switch (Form) { 479 default: llvm_unreachable("Unhandled form"); 480 case X86Local::PrefixByte: 481 return; 482 case X86Local::RawFrmSrc: 483 HANDLE_OPERAND(relocation); 484 return; 485 case X86Local::RawFrmDst: 486 HANDLE_OPERAND(relocation); 487 return; 488 case X86Local::RawFrmDstSrc: 489 HANDLE_OPERAND(relocation); 490 HANDLE_OPERAND(relocation); 491 return; 492 case X86Local::RawFrm: 493 // Operand 1 (optional) is an address or immediate. 494 assert(numPhysicalOperands <= 1 && 495 "Unexpected number of operands for RawFrm"); 496 HANDLE_OPTIONAL(relocation) 497 break; 498 case X86Local::RawFrmMemOffs: 499 // Operand 1 is an address. 500 HANDLE_OPERAND(relocation); 501 break; 502 case X86Local::AddRegFrm: 503 // Operand 1 is added to the opcode. 504 // Operand 2 (optional) is an address. 505 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 506 "Unexpected number of operands for AddRegFrm"); 507 HANDLE_OPERAND(opcodeModifier) 508 HANDLE_OPTIONAL(relocation) 509 break; 510 case X86Local::AddCCFrm: 511 // Operand 1 (optional) is an address or immediate. 512 assert(numPhysicalOperands == 2 && 513 "Unexpected number of operands for AddCCFrm"); 514 HANDLE_OPERAND(relocation) 515 HANDLE_OPERAND(opcodeModifier) 516 break; 517 case X86Local::MRMDestReg: 518 // Operand 1 is a register operand in the R/M field. 519 // - In AVX512 there may be a mask operand here - 520 // Operand 2 is a register operand in the Reg/Opcode field. 521 // - In AVX, there is a register operand in the VEX.vvvv field here - 522 // Operand 3 (optional) is an immediate. 523 assert(numPhysicalOperands >= 2 + additionalOperands && 524 numPhysicalOperands <= 3 + additionalOperands && 525 "Unexpected number of operands for MRMDestRegFrm"); 526 527 HANDLE_OPERAND(rmRegister) 528 if (HasEVEX_K) 529 HANDLE_OPERAND(writemaskRegister) 530 531 if (HasVEX_4V) 532 // FIXME: In AVX, the register below becomes the one encoded 533 // in ModRMVEX and the one above the one in the VEX.VVVV field 534 HANDLE_OPERAND(vvvvRegister) 535 536 HANDLE_OPERAND(roRegister) 537 HANDLE_OPTIONAL(immediate) 538 break; 539 case X86Local::MRMDestMem: 540 case X86Local::MRMDestMemFSIB: 541 // Operand 1 is a memory operand (possibly SIB-extended) 542 // Operand 2 is a register operand in the Reg/Opcode field. 543 // - In AVX, there is a register operand in the VEX.vvvv field here - 544 // Operand 3 (optional) is an immediate. 545 assert(numPhysicalOperands >= 2 + additionalOperands && 546 numPhysicalOperands <= 3 + additionalOperands && 547 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 548 549 HANDLE_OPERAND(memory) 550 551 if (HasEVEX_K) 552 HANDLE_OPERAND(writemaskRegister) 553 554 if (HasVEX_4V) 555 // FIXME: In AVX, the register below becomes the one encoded 556 // in ModRMVEX and the one above the one in the VEX.VVVV field 557 HANDLE_OPERAND(vvvvRegister) 558 559 HANDLE_OPERAND(roRegister) 560 HANDLE_OPTIONAL(immediate) 561 break; 562 case X86Local::MRMSrcReg: 563 // Operand 1 is a register operand in the Reg/Opcode field. 564 // Operand 2 is a register operand in the R/M field. 565 // - In AVX, there is a register operand in the VEX.vvvv field here - 566 // Operand 3 (optional) is an immediate. 567 // Operand 4 (optional) is an immediate. 568 569 assert(numPhysicalOperands >= 2 + additionalOperands && 570 numPhysicalOperands <= 4 + additionalOperands && 571 "Unexpected number of operands for MRMSrcRegFrm"); 572 573 HANDLE_OPERAND(roRegister) 574 575 if (HasEVEX_K) 576 HANDLE_OPERAND(writemaskRegister) 577 578 if (HasVEX_4V) 579 // FIXME: In AVX, the register below becomes the one encoded 580 // in ModRMVEX and the one above the one in the VEX.VVVV field 581 HANDLE_OPERAND(vvvvRegister) 582 583 HANDLE_OPERAND(rmRegister) 584 HANDLE_OPTIONAL(immediate) 585 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 586 break; 587 case X86Local::MRMSrcReg4VOp3: 588 assert(numPhysicalOperands == 3 && 589 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 590 HANDLE_OPERAND(roRegister) 591 HANDLE_OPERAND(rmRegister) 592 HANDLE_OPERAND(vvvvRegister) 593 break; 594 case X86Local::MRMSrcRegOp4: 595 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 596 "Unexpected number of operands for MRMSrcRegOp4Frm"); 597 HANDLE_OPERAND(roRegister) 598 HANDLE_OPERAND(vvvvRegister) 599 HANDLE_OPERAND(immediate) // Register in imm[7:4] 600 HANDLE_OPERAND(rmRegister) 601 HANDLE_OPTIONAL(immediate) 602 break; 603 case X86Local::MRMSrcRegCC: 604 assert(numPhysicalOperands == 3 && 605 "Unexpected number of operands for MRMSrcRegCC"); 606 HANDLE_OPERAND(roRegister) 607 HANDLE_OPERAND(rmRegister) 608 HANDLE_OPERAND(opcodeModifier) 609 break; 610 case X86Local::MRMSrcMem: 611 case X86Local::MRMSrcMemFSIB: 612 // Operand 1 is a register operand in the Reg/Opcode field. 613 // Operand 2 is a memory operand (possibly SIB-extended) 614 // - In AVX, there is a register operand in the VEX.vvvv field here - 615 // Operand 3 (optional) is an immediate. 616 617 assert(numPhysicalOperands >= 2 + additionalOperands && 618 numPhysicalOperands <= 4 + additionalOperands && 619 "Unexpected number of operands for MRMSrcMemFrm"); 620 621 HANDLE_OPERAND(roRegister) 622 623 if (HasEVEX_K) 624 HANDLE_OPERAND(writemaskRegister) 625 626 if (HasVEX_4V) 627 // FIXME: In AVX, the register below becomes the one encoded 628 // in ModRMVEX and the one above the one in the VEX.VVVV field 629 HANDLE_OPERAND(vvvvRegister) 630 631 HANDLE_OPERAND(memory) 632 HANDLE_OPTIONAL(immediate) 633 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 634 break; 635 case X86Local::MRMSrcMem4VOp3: 636 assert(numPhysicalOperands == 3 && 637 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 638 HANDLE_OPERAND(roRegister) 639 HANDLE_OPERAND(memory) 640 HANDLE_OPERAND(vvvvRegister) 641 break; 642 case X86Local::MRMSrcMemOp4: 643 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 644 "Unexpected number of operands for MRMSrcMemOp4Frm"); 645 HANDLE_OPERAND(roRegister) 646 HANDLE_OPERAND(vvvvRegister) 647 HANDLE_OPERAND(immediate) // Register in imm[7:4] 648 HANDLE_OPERAND(memory) 649 HANDLE_OPTIONAL(immediate) 650 break; 651 case X86Local::MRMSrcMemCC: 652 assert(numPhysicalOperands == 3 && 653 "Unexpected number of operands for MRMSrcMemCC"); 654 HANDLE_OPERAND(roRegister) 655 HANDLE_OPERAND(memory) 656 HANDLE_OPERAND(opcodeModifier) 657 break; 658 case X86Local::MRMXrCC: 659 assert(numPhysicalOperands == 2 && 660 "Unexpected number of operands for MRMXrCC"); 661 HANDLE_OPERAND(rmRegister) 662 HANDLE_OPERAND(opcodeModifier) 663 break; 664 case X86Local::MRMr0: 665 // Operand 1 is a register operand in the R/M field. 666 HANDLE_OPERAND(roRegister) 667 break; 668 case X86Local::MRMXr: 669 case X86Local::MRM0r: 670 case X86Local::MRM1r: 671 case X86Local::MRM2r: 672 case X86Local::MRM3r: 673 case X86Local::MRM4r: 674 case X86Local::MRM5r: 675 case X86Local::MRM6r: 676 case X86Local::MRM7r: 677 // Operand 1 is a register operand in the R/M field. 678 // Operand 2 (optional) is an immediate or relocation. 679 // Operand 3 (optional) is an immediate. 680 assert(numPhysicalOperands >= 0 + additionalOperands && 681 numPhysicalOperands <= 3 + additionalOperands && 682 "Unexpected number of operands for MRMnr"); 683 684 if (HasVEX_4V) 685 HANDLE_OPERAND(vvvvRegister) 686 687 if (HasEVEX_K) 688 HANDLE_OPERAND(writemaskRegister) 689 HANDLE_OPTIONAL(rmRegister) 690 HANDLE_OPTIONAL(relocation) 691 HANDLE_OPTIONAL(immediate) 692 break; 693 case X86Local::MRMXmCC: 694 assert(numPhysicalOperands == 2 && 695 "Unexpected number of operands for MRMXm"); 696 HANDLE_OPERAND(memory) 697 HANDLE_OPERAND(opcodeModifier) 698 break; 699 case X86Local::MRMXm: 700 case X86Local::MRM0m: 701 case X86Local::MRM1m: 702 case X86Local::MRM2m: 703 case X86Local::MRM3m: 704 case X86Local::MRM4m: 705 case X86Local::MRM5m: 706 case X86Local::MRM6m: 707 case X86Local::MRM7m: 708 // Operand 1 is a memory operand (possibly SIB-extended) 709 // Operand 2 (optional) is an immediate or relocation. 710 assert(numPhysicalOperands >= 1 + additionalOperands && 711 numPhysicalOperands <= 2 + additionalOperands && 712 "Unexpected number of operands for MRMnm"); 713 714 if (HasVEX_4V) 715 HANDLE_OPERAND(vvvvRegister) 716 if (HasEVEX_K) 717 HANDLE_OPERAND(writemaskRegister) 718 HANDLE_OPERAND(memory) 719 HANDLE_OPTIONAL(relocation) 720 break; 721 case X86Local::RawFrmImm8: 722 // operand 1 is a 16-bit immediate 723 // operand 2 is an 8-bit immediate 724 assert(numPhysicalOperands == 2 && 725 "Unexpected number of operands for X86Local::RawFrmImm8"); 726 HANDLE_OPERAND(immediate) 727 HANDLE_OPERAND(immediate) 728 break; 729 case X86Local::RawFrmImm16: 730 // operand 1 is a 16-bit immediate 731 // operand 2 is a 16-bit immediate 732 HANDLE_OPERAND(immediate) 733 HANDLE_OPERAND(immediate) 734 break; 735 case X86Local::MRM0X: 736 case X86Local::MRM1X: 737 case X86Local::MRM2X: 738 case X86Local::MRM3X: 739 case X86Local::MRM4X: 740 case X86Local::MRM5X: 741 case X86Local::MRM6X: 742 case X86Local::MRM7X: 743 #define MAP(from, to) case X86Local::MRM_##from: 744 X86_INSTR_MRM_MAPPING 745 #undef MAP 746 HANDLE_OPTIONAL(relocation) 747 break; 748 } 749 750 #undef HANDLE_OPERAND 751 #undef HANDLE_OPTIONAL 752 } 753 754 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 755 // Special cases where the LLVM tables are not complete 756 757 #define MAP(from, to) \ 758 case X86Local::MRM_##from: 759 760 llvm::Optional<OpcodeType> opcodeType; 761 switch (OpMap) { 762 default: llvm_unreachable("Invalid map!"); 763 case X86Local::OB: opcodeType = ONEBYTE; break; 764 case X86Local::TB: opcodeType = TWOBYTE; break; 765 case X86Local::T8: opcodeType = THREEBYTE_38; break; 766 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 767 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 768 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 769 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 770 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 771 case X86Local::T_MAP5: opcodeType = MAP5; break; 772 case X86Local::T_MAP6: opcodeType = MAP6; break; 773 } 774 775 std::unique_ptr<ModRMFilter> filter; 776 switch (Form) { 777 default: llvm_unreachable("Invalid form!"); 778 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 779 case X86Local::RawFrm: 780 case X86Local::AddRegFrm: 781 case X86Local::RawFrmMemOffs: 782 case X86Local::RawFrmSrc: 783 case X86Local::RawFrmDst: 784 case X86Local::RawFrmDstSrc: 785 case X86Local::RawFrmImm8: 786 case X86Local::RawFrmImm16: 787 case X86Local::AddCCFrm: 788 case X86Local::PrefixByte: 789 filter = std::make_unique<DumbFilter>(); 790 break; 791 case X86Local::MRMDestReg: 792 case X86Local::MRMSrcReg: 793 case X86Local::MRMSrcReg4VOp3: 794 case X86Local::MRMSrcRegOp4: 795 case X86Local::MRMSrcRegCC: 796 case X86Local::MRMXrCC: 797 case X86Local::MRMXr: 798 filter = std::make_unique<ModFilter>(true); 799 break; 800 case X86Local::MRMDestMem: 801 case X86Local::MRMDestMemFSIB: 802 case X86Local::MRMSrcMem: 803 case X86Local::MRMSrcMemFSIB: 804 case X86Local::MRMSrcMem4VOp3: 805 case X86Local::MRMSrcMemOp4: 806 case X86Local::MRMSrcMemCC: 807 case X86Local::MRMXmCC: 808 case X86Local::MRMXm: 809 filter = std::make_unique<ModFilter>(false); 810 break; 811 case X86Local::MRM0r: case X86Local::MRM1r: 812 case X86Local::MRM2r: case X86Local::MRM3r: 813 case X86Local::MRM4r: case X86Local::MRM5r: 814 case X86Local::MRM6r: case X86Local::MRM7r: 815 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 816 break; 817 case X86Local::MRM0X: case X86Local::MRM1X: 818 case X86Local::MRM2X: case X86Local::MRM3X: 819 case X86Local::MRM4X: case X86Local::MRM5X: 820 case X86Local::MRM6X: case X86Local::MRM7X: 821 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 822 break; 823 case X86Local::MRMr0: 824 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 825 break; 826 case X86Local::MRM0m: case X86Local::MRM1m: 827 case X86Local::MRM2m: case X86Local::MRM3m: 828 case X86Local::MRM4m: case X86Local::MRM5m: 829 case X86Local::MRM6m: case X86Local::MRM7m: 830 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 831 break; 832 X86_INSTR_MRM_MAPPING 833 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 834 break; 835 } // switch (Form) 836 837 uint8_t opcodeToSet = Opcode; 838 839 unsigned AddressSize = 0; 840 switch (AdSize) { 841 case X86Local::AdSize16: AddressSize = 16; break; 842 case X86Local::AdSize32: AddressSize = 32; break; 843 case X86Local::AdSize64: AddressSize = 64; break; 844 } 845 846 assert(opcodeType && "Opcode type not set"); 847 assert(filter && "Filter not set"); 848 849 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 850 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 851 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { 852 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; 853 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 854 855 uint8_t currentOpcode; 856 857 for (currentOpcode = opcodeToSet; 858 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode) 859 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 860 UID, Is32Bit, OpPrefix == 0, 861 IgnoresVEX_L || EncodeRC, 862 IgnoresVEX_W, AddressSize); 863 } else { 864 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 865 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 866 IgnoresVEX_W, AddressSize); 867 } 868 869 #undef MAP 870 } 871 872 #define TYPE(str, type) if (s == str) return type; 873 OperandType RecognizableInstr::typeFromString(const std::string &s, 874 bool hasREX_WPrefix, 875 uint8_t OpSize) { 876 if(hasREX_WPrefix) { 877 // For instructions with a REX_W prefix, a declared 32-bit register encoding 878 // is special. 879 TYPE("GR32", TYPE_R32) 880 } 881 if(OpSize == X86Local::OpSize16) { 882 // For OpSize16 instructions, a declared 16-bit register or 883 // immediate encoding is special. 884 TYPE("GR16", TYPE_Rv) 885 } else if(OpSize == X86Local::OpSize32) { 886 // For OpSize32 instructions, a declared 32-bit register or 887 // immediate encoding is special. 888 TYPE("GR32", TYPE_Rv) 889 } 890 TYPE("i16mem", TYPE_M) 891 TYPE("i16imm", TYPE_IMM) 892 TYPE("i16i8imm", TYPE_IMM) 893 TYPE("GR16", TYPE_R16) 894 TYPE("GR16orGR32orGR64", TYPE_R16) 895 TYPE("i32mem", TYPE_M) 896 TYPE("i32imm", TYPE_IMM) 897 TYPE("i32i8imm", TYPE_IMM) 898 TYPE("GR32", TYPE_R32) 899 TYPE("GR32orGR64", TYPE_R32) 900 TYPE("i64mem", TYPE_M) 901 TYPE("i64i32imm", TYPE_IMM) 902 TYPE("i64i8imm", TYPE_IMM) 903 TYPE("GR64", TYPE_R64) 904 TYPE("i8mem", TYPE_M) 905 TYPE("i8imm", TYPE_IMM) 906 TYPE("u4imm", TYPE_UIMM8) 907 TYPE("u8imm", TYPE_UIMM8) 908 TYPE("i16u8imm", TYPE_UIMM8) 909 TYPE("i32u8imm", TYPE_UIMM8) 910 TYPE("i64u8imm", TYPE_UIMM8) 911 TYPE("GR8", TYPE_R8) 912 TYPE("VR128", TYPE_XMM) 913 TYPE("VR128X", TYPE_XMM) 914 TYPE("f128mem", TYPE_M) 915 TYPE("f256mem", TYPE_M) 916 TYPE("f512mem", TYPE_M) 917 TYPE("FR128", TYPE_XMM) 918 TYPE("FR64", TYPE_XMM) 919 TYPE("FR64X", TYPE_XMM) 920 TYPE("f64mem", TYPE_M) 921 TYPE("sdmem", TYPE_M) 922 TYPE("FR16X", TYPE_XMM) 923 TYPE("FR32", TYPE_XMM) 924 TYPE("FR32X", TYPE_XMM) 925 TYPE("f32mem", TYPE_M) 926 TYPE("f16mem", TYPE_M) 927 TYPE("ssmem", TYPE_M) 928 TYPE("shmem", TYPE_M) 929 TYPE("RST", TYPE_ST) 930 TYPE("RSTi", TYPE_ST) 931 TYPE("i128mem", TYPE_M) 932 TYPE("i256mem", TYPE_M) 933 TYPE("i512mem", TYPE_M) 934 TYPE("i64i32imm_brtarget", TYPE_REL) 935 TYPE("i16imm_brtarget", TYPE_REL) 936 TYPE("i32imm_brtarget", TYPE_REL) 937 TYPE("ccode", TYPE_IMM) 938 TYPE("AVX512RC", TYPE_IMM) 939 TYPE("brtarget32", TYPE_REL) 940 TYPE("brtarget16", TYPE_REL) 941 TYPE("brtarget8", TYPE_REL) 942 TYPE("f80mem", TYPE_M) 943 TYPE("lea64_32mem", TYPE_M) 944 TYPE("lea64mem", TYPE_M) 945 TYPE("VR64", TYPE_MM64) 946 TYPE("i64imm", TYPE_IMM) 947 TYPE("anymem", TYPE_M) 948 TYPE("opaquemem", TYPE_M) 949 TYPE("sibmem", TYPE_MSIB) 950 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 951 TYPE("DEBUG_REG", TYPE_DEBUGREG) 952 TYPE("CONTROL_REG", TYPE_CONTROLREG) 953 TYPE("srcidx8", TYPE_SRCIDX) 954 TYPE("srcidx16", TYPE_SRCIDX) 955 TYPE("srcidx32", TYPE_SRCIDX) 956 TYPE("srcidx64", TYPE_SRCIDX) 957 TYPE("dstidx8", TYPE_DSTIDX) 958 TYPE("dstidx16", TYPE_DSTIDX) 959 TYPE("dstidx32", TYPE_DSTIDX) 960 TYPE("dstidx64", TYPE_DSTIDX) 961 TYPE("offset16_8", TYPE_MOFFS) 962 TYPE("offset16_16", TYPE_MOFFS) 963 TYPE("offset16_32", TYPE_MOFFS) 964 TYPE("offset32_8", TYPE_MOFFS) 965 TYPE("offset32_16", TYPE_MOFFS) 966 TYPE("offset32_32", TYPE_MOFFS) 967 TYPE("offset32_64", TYPE_MOFFS) 968 TYPE("offset64_8", TYPE_MOFFS) 969 TYPE("offset64_16", TYPE_MOFFS) 970 TYPE("offset64_32", TYPE_MOFFS) 971 TYPE("offset64_64", TYPE_MOFFS) 972 TYPE("VR256", TYPE_YMM) 973 TYPE("VR256X", TYPE_YMM) 974 TYPE("VR512", TYPE_ZMM) 975 TYPE("VK1", TYPE_VK) 976 TYPE("VK1WM", TYPE_VK) 977 TYPE("VK2", TYPE_VK) 978 TYPE("VK2WM", TYPE_VK) 979 TYPE("VK4", TYPE_VK) 980 TYPE("VK4WM", TYPE_VK) 981 TYPE("VK8", TYPE_VK) 982 TYPE("VK8WM", TYPE_VK) 983 TYPE("VK16", TYPE_VK) 984 TYPE("VK16WM", TYPE_VK) 985 TYPE("VK32", TYPE_VK) 986 TYPE("VK32WM", TYPE_VK) 987 TYPE("VK64", TYPE_VK) 988 TYPE("VK64WM", TYPE_VK) 989 TYPE("VK1Pair", TYPE_VK_PAIR) 990 TYPE("VK2Pair", TYPE_VK_PAIR) 991 TYPE("VK4Pair", TYPE_VK_PAIR) 992 TYPE("VK8Pair", TYPE_VK_PAIR) 993 TYPE("VK16Pair", TYPE_VK_PAIR) 994 TYPE("vx64mem", TYPE_MVSIBX) 995 TYPE("vx128mem", TYPE_MVSIBX) 996 TYPE("vx256mem", TYPE_MVSIBX) 997 TYPE("vy128mem", TYPE_MVSIBY) 998 TYPE("vy256mem", TYPE_MVSIBY) 999 TYPE("vx64xmem", TYPE_MVSIBX) 1000 TYPE("vx128xmem", TYPE_MVSIBX) 1001 TYPE("vx256xmem", TYPE_MVSIBX) 1002 TYPE("vy128xmem", TYPE_MVSIBY) 1003 TYPE("vy256xmem", TYPE_MVSIBY) 1004 TYPE("vy512xmem", TYPE_MVSIBY) 1005 TYPE("vz256mem", TYPE_MVSIBZ) 1006 TYPE("vz512mem", TYPE_MVSIBZ) 1007 TYPE("BNDR", TYPE_BNDR) 1008 TYPE("TILE", TYPE_TMM) 1009 errs() << "Unhandled type string " << s << "\n"; 1010 llvm_unreachable("Unhandled type string"); 1011 } 1012 #undef TYPE 1013 1014 #define ENCODING(str, encoding) if (s == str) return encoding; 1015 OperandEncoding 1016 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1017 uint8_t OpSize) { 1018 if(OpSize != X86Local::OpSize16) { 1019 // For instructions without an OpSize prefix, a declared 16-bit register or 1020 // immediate encoding is special. 1021 ENCODING("i16imm", ENCODING_IW) 1022 } 1023 ENCODING("i32i8imm", ENCODING_IB) 1024 ENCODING("AVX512RC", ENCODING_IRC) 1025 ENCODING("i16imm", ENCODING_Iv) 1026 ENCODING("i16i8imm", ENCODING_IB) 1027 ENCODING("i32imm", ENCODING_Iv) 1028 ENCODING("i64i32imm", ENCODING_ID) 1029 ENCODING("i64i8imm", ENCODING_IB) 1030 ENCODING("i8imm", ENCODING_IB) 1031 ENCODING("u4imm", ENCODING_IB) 1032 ENCODING("u8imm", ENCODING_IB) 1033 ENCODING("i16u8imm", ENCODING_IB) 1034 ENCODING("i32u8imm", ENCODING_IB) 1035 ENCODING("i64u8imm", ENCODING_IB) 1036 // This is not a typo. Instructions like BLENDVPD put 1037 // register IDs in 8-bit immediates nowadays. 1038 ENCODING("FR32", ENCODING_IB) 1039 ENCODING("FR64", ENCODING_IB) 1040 ENCODING("FR128", ENCODING_IB) 1041 ENCODING("VR128", ENCODING_IB) 1042 ENCODING("VR256", ENCODING_IB) 1043 ENCODING("FR16X", ENCODING_IB) 1044 ENCODING("FR32X", ENCODING_IB) 1045 ENCODING("FR64X", ENCODING_IB) 1046 ENCODING("VR128X", ENCODING_IB) 1047 ENCODING("VR256X", ENCODING_IB) 1048 ENCODING("VR512", ENCODING_IB) 1049 ENCODING("TILE", ENCODING_IB) 1050 errs() << "Unhandled immediate encoding " << s << "\n"; 1051 llvm_unreachable("Unhandled immediate encoding"); 1052 } 1053 1054 OperandEncoding 1055 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1056 uint8_t OpSize) { 1057 ENCODING("RST", ENCODING_FP) 1058 ENCODING("RSTi", ENCODING_FP) 1059 ENCODING("GR16", ENCODING_RM) 1060 ENCODING("GR16orGR32orGR64",ENCODING_RM) 1061 ENCODING("GR32", ENCODING_RM) 1062 ENCODING("GR32orGR64", ENCODING_RM) 1063 ENCODING("GR64", ENCODING_RM) 1064 ENCODING("GR8", ENCODING_RM) 1065 ENCODING("VR128", ENCODING_RM) 1066 ENCODING("VR128X", ENCODING_RM) 1067 ENCODING("FR128", ENCODING_RM) 1068 ENCODING("FR64", ENCODING_RM) 1069 ENCODING("FR32", ENCODING_RM) 1070 ENCODING("FR64X", ENCODING_RM) 1071 ENCODING("FR32X", ENCODING_RM) 1072 ENCODING("FR16X", ENCODING_RM) 1073 ENCODING("VR64", ENCODING_RM) 1074 ENCODING("VR256", ENCODING_RM) 1075 ENCODING("VR256X", ENCODING_RM) 1076 ENCODING("VR512", ENCODING_RM) 1077 ENCODING("VK1", ENCODING_RM) 1078 ENCODING("VK2", ENCODING_RM) 1079 ENCODING("VK4", ENCODING_RM) 1080 ENCODING("VK8", ENCODING_RM) 1081 ENCODING("VK16", ENCODING_RM) 1082 ENCODING("VK32", ENCODING_RM) 1083 ENCODING("VK64", ENCODING_RM) 1084 ENCODING("BNDR", ENCODING_RM) 1085 ENCODING("TILE", ENCODING_RM) 1086 errs() << "Unhandled R/M register encoding " << s << "\n"; 1087 llvm_unreachable("Unhandled R/M register encoding"); 1088 } 1089 1090 OperandEncoding 1091 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1092 uint8_t OpSize) { 1093 ENCODING("GR16", ENCODING_REG) 1094 ENCODING("GR16orGR32orGR64",ENCODING_REG) 1095 ENCODING("GR32", ENCODING_REG) 1096 ENCODING("GR32orGR64", ENCODING_REG) 1097 ENCODING("GR64", ENCODING_REG) 1098 ENCODING("GR8", ENCODING_REG) 1099 ENCODING("VR128", ENCODING_REG) 1100 ENCODING("FR128", ENCODING_REG) 1101 ENCODING("FR64", ENCODING_REG) 1102 ENCODING("FR32", ENCODING_REG) 1103 ENCODING("VR64", ENCODING_REG) 1104 ENCODING("SEGMENT_REG", ENCODING_REG) 1105 ENCODING("DEBUG_REG", ENCODING_REG) 1106 ENCODING("CONTROL_REG", ENCODING_REG) 1107 ENCODING("VR256", ENCODING_REG) 1108 ENCODING("VR256X", ENCODING_REG) 1109 ENCODING("VR128X", ENCODING_REG) 1110 ENCODING("FR64X", ENCODING_REG) 1111 ENCODING("FR32X", ENCODING_REG) 1112 ENCODING("FR16X", ENCODING_REG) 1113 ENCODING("VR512", ENCODING_REG) 1114 ENCODING("VK1", ENCODING_REG) 1115 ENCODING("VK2", ENCODING_REG) 1116 ENCODING("VK4", ENCODING_REG) 1117 ENCODING("VK8", ENCODING_REG) 1118 ENCODING("VK16", ENCODING_REG) 1119 ENCODING("VK32", ENCODING_REG) 1120 ENCODING("VK64", ENCODING_REG) 1121 ENCODING("VK1Pair", ENCODING_REG) 1122 ENCODING("VK2Pair", ENCODING_REG) 1123 ENCODING("VK4Pair", ENCODING_REG) 1124 ENCODING("VK8Pair", ENCODING_REG) 1125 ENCODING("VK16Pair", ENCODING_REG) 1126 ENCODING("VK1WM", ENCODING_REG) 1127 ENCODING("VK2WM", ENCODING_REG) 1128 ENCODING("VK4WM", ENCODING_REG) 1129 ENCODING("VK8WM", ENCODING_REG) 1130 ENCODING("VK16WM", ENCODING_REG) 1131 ENCODING("VK32WM", ENCODING_REG) 1132 ENCODING("VK64WM", ENCODING_REG) 1133 ENCODING("BNDR", ENCODING_REG) 1134 ENCODING("TILE", ENCODING_REG) 1135 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1136 llvm_unreachable("Unhandled reg/opcode register encoding"); 1137 } 1138 1139 OperandEncoding 1140 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1141 uint8_t OpSize) { 1142 ENCODING("GR32", ENCODING_VVVV) 1143 ENCODING("GR64", ENCODING_VVVV) 1144 ENCODING("FR32", ENCODING_VVVV) 1145 ENCODING("FR128", ENCODING_VVVV) 1146 ENCODING("FR64", ENCODING_VVVV) 1147 ENCODING("VR128", ENCODING_VVVV) 1148 ENCODING("VR256", ENCODING_VVVV) 1149 ENCODING("FR16X", ENCODING_VVVV) 1150 ENCODING("FR32X", ENCODING_VVVV) 1151 ENCODING("FR64X", ENCODING_VVVV) 1152 ENCODING("VR128X", ENCODING_VVVV) 1153 ENCODING("VR256X", ENCODING_VVVV) 1154 ENCODING("VR512", ENCODING_VVVV) 1155 ENCODING("VK1", ENCODING_VVVV) 1156 ENCODING("VK2", ENCODING_VVVV) 1157 ENCODING("VK4", ENCODING_VVVV) 1158 ENCODING("VK8", ENCODING_VVVV) 1159 ENCODING("VK16", ENCODING_VVVV) 1160 ENCODING("VK32", ENCODING_VVVV) 1161 ENCODING("VK64", ENCODING_VVVV) 1162 ENCODING("TILE", ENCODING_VVVV) 1163 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1164 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1165 } 1166 1167 OperandEncoding 1168 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1169 uint8_t OpSize) { 1170 ENCODING("VK1WM", ENCODING_WRITEMASK) 1171 ENCODING("VK2WM", ENCODING_WRITEMASK) 1172 ENCODING("VK4WM", ENCODING_WRITEMASK) 1173 ENCODING("VK8WM", ENCODING_WRITEMASK) 1174 ENCODING("VK16WM", ENCODING_WRITEMASK) 1175 ENCODING("VK32WM", ENCODING_WRITEMASK) 1176 ENCODING("VK64WM", ENCODING_WRITEMASK) 1177 errs() << "Unhandled mask register encoding " << s << "\n"; 1178 llvm_unreachable("Unhandled mask register encoding"); 1179 } 1180 1181 OperandEncoding 1182 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1183 uint8_t OpSize) { 1184 ENCODING("i16mem", ENCODING_RM) 1185 ENCODING("i32mem", ENCODING_RM) 1186 ENCODING("i64mem", ENCODING_RM) 1187 ENCODING("i8mem", ENCODING_RM) 1188 ENCODING("shmem", ENCODING_RM) 1189 ENCODING("ssmem", ENCODING_RM) 1190 ENCODING("sdmem", ENCODING_RM) 1191 ENCODING("f128mem", ENCODING_RM) 1192 ENCODING("f256mem", ENCODING_RM) 1193 ENCODING("f512mem", ENCODING_RM) 1194 ENCODING("f64mem", ENCODING_RM) 1195 ENCODING("f32mem", ENCODING_RM) 1196 ENCODING("f16mem", ENCODING_RM) 1197 ENCODING("i128mem", ENCODING_RM) 1198 ENCODING("i256mem", ENCODING_RM) 1199 ENCODING("i512mem", ENCODING_RM) 1200 ENCODING("f80mem", ENCODING_RM) 1201 ENCODING("lea64_32mem", ENCODING_RM) 1202 ENCODING("lea64mem", ENCODING_RM) 1203 ENCODING("anymem", ENCODING_RM) 1204 ENCODING("opaquemem", ENCODING_RM) 1205 ENCODING("sibmem", ENCODING_SIB) 1206 ENCODING("vx64mem", ENCODING_VSIB) 1207 ENCODING("vx128mem", ENCODING_VSIB) 1208 ENCODING("vx256mem", ENCODING_VSIB) 1209 ENCODING("vy128mem", ENCODING_VSIB) 1210 ENCODING("vy256mem", ENCODING_VSIB) 1211 ENCODING("vx64xmem", ENCODING_VSIB) 1212 ENCODING("vx128xmem", ENCODING_VSIB) 1213 ENCODING("vx256xmem", ENCODING_VSIB) 1214 ENCODING("vy128xmem", ENCODING_VSIB) 1215 ENCODING("vy256xmem", ENCODING_VSIB) 1216 ENCODING("vy512xmem", ENCODING_VSIB) 1217 ENCODING("vz256mem", ENCODING_VSIB) 1218 ENCODING("vz512mem", ENCODING_VSIB) 1219 errs() << "Unhandled memory encoding " << s << "\n"; 1220 llvm_unreachable("Unhandled memory encoding"); 1221 } 1222 1223 OperandEncoding 1224 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1225 uint8_t OpSize) { 1226 if(OpSize != X86Local::OpSize16) { 1227 // For instructions without an OpSize prefix, a declared 16-bit register or 1228 // immediate encoding is special. 1229 ENCODING("i16imm", ENCODING_IW) 1230 } 1231 ENCODING("i16imm", ENCODING_Iv) 1232 ENCODING("i16i8imm", ENCODING_IB) 1233 ENCODING("i32imm", ENCODING_Iv) 1234 ENCODING("i32i8imm", ENCODING_IB) 1235 ENCODING("i64i32imm", ENCODING_ID) 1236 ENCODING("i64i8imm", ENCODING_IB) 1237 ENCODING("i8imm", ENCODING_IB) 1238 ENCODING("u8imm", ENCODING_IB) 1239 ENCODING("i16u8imm", ENCODING_IB) 1240 ENCODING("i32u8imm", ENCODING_IB) 1241 ENCODING("i64u8imm", ENCODING_IB) 1242 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1243 ENCODING("i16imm_brtarget", ENCODING_IW) 1244 ENCODING("i32imm_brtarget", ENCODING_ID) 1245 ENCODING("brtarget32", ENCODING_ID) 1246 ENCODING("brtarget16", ENCODING_IW) 1247 ENCODING("brtarget8", ENCODING_IB) 1248 ENCODING("i64imm", ENCODING_IO) 1249 ENCODING("offset16_8", ENCODING_Ia) 1250 ENCODING("offset16_16", ENCODING_Ia) 1251 ENCODING("offset16_32", ENCODING_Ia) 1252 ENCODING("offset32_8", ENCODING_Ia) 1253 ENCODING("offset32_16", ENCODING_Ia) 1254 ENCODING("offset32_32", ENCODING_Ia) 1255 ENCODING("offset32_64", ENCODING_Ia) 1256 ENCODING("offset64_8", ENCODING_Ia) 1257 ENCODING("offset64_16", ENCODING_Ia) 1258 ENCODING("offset64_32", ENCODING_Ia) 1259 ENCODING("offset64_64", ENCODING_Ia) 1260 ENCODING("srcidx8", ENCODING_SI) 1261 ENCODING("srcidx16", ENCODING_SI) 1262 ENCODING("srcidx32", ENCODING_SI) 1263 ENCODING("srcidx64", ENCODING_SI) 1264 ENCODING("dstidx8", ENCODING_DI) 1265 ENCODING("dstidx16", ENCODING_DI) 1266 ENCODING("dstidx32", ENCODING_DI) 1267 ENCODING("dstidx64", ENCODING_DI) 1268 errs() << "Unhandled relocation encoding " << s << "\n"; 1269 llvm_unreachable("Unhandled relocation encoding"); 1270 } 1271 1272 OperandEncoding 1273 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1274 uint8_t OpSize) { 1275 ENCODING("GR32", ENCODING_Rv) 1276 ENCODING("GR64", ENCODING_RO) 1277 ENCODING("GR16", ENCODING_Rv) 1278 ENCODING("GR8", ENCODING_RB) 1279 ENCODING("ccode", ENCODING_CC) 1280 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1281 llvm_unreachable("Unhandled opcode modifier encoding"); 1282 } 1283 #undef ENCODING 1284