| 12e4ec5d | 27-Nov-2024 |
Meera Patel <[email protected]> |
drm/amd/display: initialize uninitialized variable
[WHY] There is one uninitialized variable in file dc/hwss/dcn401/dcn401_hwseq.c, which trigger com compile warnings.
[HOW] Initialize the unininit
drm/amd/display: initialize uninitialized variable
[WHY] There is one uninitialized variable in file dc/hwss/dcn401/dcn401_hwseq.c, which trigger com compile warnings.
[HOW] Initialize the unininitialized variable.
Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Ariel Bernstein <[email protected]> Signed-off-by: Meera Patel <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
show more ...
|
| df60dcf5 | 16-Sep-2024 |
Ilya Bakoulin <[email protected]> |
drm/amd/display: Add 3DLUT FL HW bug workaround
[Why] There is a known HW bug that causes the internal 3DLUT fetch signal to be lost at VREADY, regardless of whether the OTG lock is being held or no
drm/amd/display: Add 3DLUT FL HW bug workaround
[Why] There is a known HW bug that causes the internal 3DLUT fetch signal to be lost at VREADY, regardless of whether the OTG lock is being held or not. A workaround is necessary to make sure that this internal signal stays up after OTG unlock.
[How] Set the 3DLUT_ENABLE bit immediately before and after the unlock. Also use VUPDATE_KEEPOUT to prevent lock transition in the region between VSTARTUP and VREADY, which could cause issues with this WA sequence.
Also including misc. 3DLUT DMA-related sequence fixes to address a few regressions causing corruption.
Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
show more ...
|