1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include "iris_core.h" 7 #include "iris_ctrls.h" 8 #include "iris_platform_common.h" 9 #include "iris_resources.h" 10 #include "iris_hfi_gen1.h" 11 #include "iris_hfi_gen1_defines.h" 12 #include "iris_vpu_common.h" 13 14 static struct platform_inst_fw_cap inst_fw_cap_sm8250[] = { 15 { 16 .cap_id = PIPE, 17 .min = PIPE_1, 18 .max = PIPE_4, 19 .step_or_mask = 1, 20 .value = PIPE_4, 21 .hfi_id = HFI_PROPERTY_PARAM_WORK_ROUTE, 22 .set = iris_set_pipe, 23 }, 24 { 25 .cap_id = STAGE, 26 .min = STAGE_1, 27 .max = STAGE_2, 28 .step_or_mask = 1, 29 .value = STAGE_2, 30 .hfi_id = HFI_PROPERTY_PARAM_WORK_MODE, 31 .set = iris_set_stage, 32 }, 33 { 34 .cap_id = DEBLOCK, 35 .min = 0, 36 .max = 1, 37 .step_or_mask = 1, 38 .value = 0, 39 .hfi_id = HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER, 40 .set = iris_set_u32, 41 }, 42 }; 43 44 static struct platform_inst_caps platform_inst_cap_sm8250 = { 45 .min_frame_width = 128, 46 .max_frame_width = 8192, 47 .min_frame_height = 128, 48 .max_frame_height = 8192, 49 .max_mbpf = 138240, 50 .mb_cycles_vsp = 25, 51 .mb_cycles_vpp = 200, 52 }; 53 54 static void iris_set_sm8250_preset_registers(struct iris_core *core) 55 { 56 writel(0x0, core->reg_base + 0xB0088); 57 } 58 59 static const struct icc_info sm8250_icc_table[] = { 60 { "cpu-cfg", 1000, 1000 }, 61 { "video-mem", 1000, 15000000 }, 62 }; 63 64 static const char * const sm8250_clk_reset_table[] = { "bus", "core" }; 65 66 static const struct bw_info sm8250_bw_table_dec[] = { 67 { ((4096 * 2160) / 256) * 60, 2403000 }, 68 { ((4096 * 2160) / 256) * 30, 1224000 }, 69 { ((1920 * 1080) / 256) * 60, 812000 }, 70 { ((1920 * 1080) / 256) * 30, 416000 }, 71 }; 72 73 static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" }; 74 75 static const char * const sm8250_opp_pd_table[] = { "mx" }; 76 77 static const struct platform_clk_data sm8250_clk_table[] = { 78 {IRIS_AXI_CLK, "iface" }, 79 {IRIS_CTRL_CLK, "core" }, 80 {IRIS_HW_CLK, "vcodec0_core" }, 81 }; 82 83 static struct tz_cp_config tz_cp_config_sm8250 = { 84 .cp_start = 0, 85 .cp_size = 0x25800000, 86 .cp_nonpixel_start = 0x01000000, 87 .cp_nonpixel_size = 0x24800000, 88 }; 89 90 static const u32 sm8250_vdec_input_config_param_default[] = { 91 HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, 92 HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, 93 HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO, 94 HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, 95 HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM, 96 HFI_PROPERTY_PARAM_FRAME_SIZE, 97 HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL, 98 HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE, 99 }; 100 101 static const u32 sm8250_dec_ip_int_buf_tbl[] = { 102 BUF_BIN, 103 BUF_SCRATCH_1, 104 }; 105 106 static const u32 sm8250_dec_op_int_buf_tbl[] = { 107 BUF_DPB, 108 }; 109 110 struct iris_platform_data sm8250_data = { 111 .get_instance = iris_hfi_gen1_get_instance, 112 .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init, 113 .init_hfi_response_ops = iris_hfi_gen1_response_ops_init, 114 .vpu_ops = &iris_vpu2_ops, 115 .set_preset_registers = iris_set_sm8250_preset_registers, 116 .icc_tbl = sm8250_icc_table, 117 .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table), 118 .clk_rst_tbl = sm8250_clk_reset_table, 119 .clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table), 120 .bw_tbl_dec = sm8250_bw_table_dec, 121 .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), 122 .pmdomain_tbl = sm8250_pmdomain_table, 123 .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table), 124 .opp_pd_tbl = sm8250_opp_pd_table, 125 .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), 126 .clk_tbl = sm8250_clk_table, 127 .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), 128 /* Upper bound of DMA address range */ 129 .dma_mask = 0xe0000000 - 1, 130 .fwname = "qcom/vpu-1.0/venus.mbn", 131 .pas_id = IRIS_PAS_ID, 132 .inst_caps = &platform_inst_cap_sm8250, 133 .inst_fw_caps = inst_fw_cap_sm8250, 134 .inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_sm8250), 135 .tz_cp_config_data = &tz_cp_config_sm8250, 136 .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, 137 .num_vpp_pipe = 4, 138 .max_session_count = 16, 139 .max_core_mbpf = (8192 * 4352) / 256, 140 .input_config_params = 141 sm8250_vdec_input_config_param_default, 142 .input_config_params_size = 143 ARRAY_SIZE(sm8250_vdec_input_config_param_default), 144 145 .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl, 146 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), 147 .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, 148 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), 149 }; 150