1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include "iris_core.h" 7 #include "iris_ctrls.h" 8 #include "iris_hfi_gen2.h" 9 #include "iris_hfi_gen2_defines.h" 10 #include "iris_platform_common.h" 11 #include "iris_vpu_common.h" 12 13 #define VIDEO_ARCH_LX 1 14 15 static struct platform_inst_fw_cap inst_fw_cap_sm8550[] = { 16 { 17 .cap_id = PROFILE, 18 .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 19 .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, 20 .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | 21 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | 22 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | 23 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | 24 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), 25 .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 26 .hfi_id = HFI_PROP_PROFILE, 27 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, 28 .set = iris_set_u32_enum, 29 }, 30 { 31 .cap_id = LEVEL, 32 .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, 33 .max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2, 34 .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | 35 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | 36 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | 37 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | 38 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | 39 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | 40 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | 41 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | 42 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | 43 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | 44 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | 45 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | 46 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | 47 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | 48 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | 49 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | 50 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | 51 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | 52 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | 53 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), 54 .value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1, 55 .hfi_id = HFI_PROP_LEVEL, 56 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, 57 .set = iris_set_u32_enum, 58 }, 59 { 60 .cap_id = INPUT_BUF_HOST_MAX_COUNT, 61 .min = DEFAULT_MAX_HOST_BUF_COUNT, 62 .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT, 63 .step_or_mask = 1, 64 .value = DEFAULT_MAX_HOST_BUF_COUNT, 65 .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT, 66 .flags = CAP_FLAG_INPUT_PORT, 67 .set = iris_set_u32, 68 }, 69 { 70 .cap_id = STAGE, 71 .min = STAGE_1, 72 .max = STAGE_2, 73 .step_or_mask = 1, 74 .value = STAGE_2, 75 .hfi_id = HFI_PROP_STAGE, 76 .set = iris_set_stage, 77 }, 78 { 79 .cap_id = PIPE, 80 .min = PIPE_1, 81 .max = PIPE_4, 82 .step_or_mask = 1, 83 .value = PIPE_4, 84 .hfi_id = HFI_PROP_PIPE, 85 .set = iris_set_pipe, 86 }, 87 { 88 .cap_id = POC, 89 .min = 0, 90 .max = 2, 91 .step_or_mask = 1, 92 .value = 1, 93 .hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE, 94 }, 95 { 96 .cap_id = CODED_FRAMES, 97 .min = CODED_FRAMES_PROGRESSIVE, 98 .max = CODED_FRAMES_PROGRESSIVE, 99 .step_or_mask = 0, 100 .value = CODED_FRAMES_PROGRESSIVE, 101 .hfi_id = HFI_PROP_CODED_FRAMES, 102 }, 103 { 104 .cap_id = BIT_DEPTH, 105 .min = BIT_DEPTH_8, 106 .max = BIT_DEPTH_8, 107 .step_or_mask = 1, 108 .value = BIT_DEPTH_8, 109 .hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH, 110 }, 111 { 112 .cap_id = RAP_FRAME, 113 .min = 0, 114 .max = 1, 115 .step_or_mask = 1, 116 .value = 1, 117 .hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME, 118 .flags = CAP_FLAG_INPUT_PORT, 119 .set = iris_set_u32, 120 }, 121 }; 122 123 static struct platform_inst_caps platform_inst_cap_sm8550 = { 124 .min_frame_width = 96, 125 .max_frame_width = 8192, 126 .min_frame_height = 96, 127 .max_frame_height = 8192, 128 .max_mbpf = (8192 * 4352) / 256, 129 .mb_cycles_vpp = 200, 130 .mb_cycles_fw = 489583, 131 .mb_cycles_fw_vpp = 66234, 132 .num_comv = 0, 133 }; 134 135 static void iris_set_sm8550_preset_registers(struct iris_core *core) 136 { 137 writel(0x0, core->reg_base + 0xB0088); 138 } 139 140 static const struct icc_info sm8550_icc_table[] = { 141 { "cpu-cfg", 1000, 1000 }, 142 { "video-mem", 1000, 15000000 }, 143 }; 144 145 static const char * const sm8550_clk_reset_table[] = { "bus" }; 146 147 static const struct bw_info sm8550_bw_table_dec[] = { 148 { ((4096 * 2160) / 256) * 60, 1608000 }, 149 { ((4096 * 2160) / 256) * 30, 826000 }, 150 { ((1920 * 1080) / 256) * 60, 567000 }, 151 { ((1920 * 1080) / 256) * 30, 294000 }, 152 }; 153 154 static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" }; 155 156 static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" }; 157 158 static const struct platform_clk_data sm8550_clk_table[] = { 159 {IRIS_AXI_CLK, "iface" }, 160 {IRIS_CTRL_CLK, "core" }, 161 {IRIS_HW_CLK, "vcodec0_core" }, 162 }; 163 164 static struct ubwc_config_data ubwc_config_sm8550 = { 165 .max_channels = 8, 166 .mal_length = 32, 167 .highest_bank_bit = 16, 168 .bank_swzl_level = 0, 169 .bank_swz2_level = 1, 170 .bank_swz3_level = 1, 171 .bank_spreading = 1, 172 }; 173 174 static struct tz_cp_config tz_cp_config_sm8550 = { 175 .cp_start = 0, 176 .cp_size = 0x25800000, 177 .cp_nonpixel_start = 0x01000000, 178 .cp_nonpixel_size = 0x24800000, 179 }; 180 181 static const u32 sm8550_vdec_input_config_params[] = { 182 HFI_PROP_BITSTREAM_RESOLUTION, 183 HFI_PROP_CROP_OFFSETS, 184 HFI_PROP_CODED_FRAMES, 185 HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, 186 HFI_PROP_PIC_ORDER_CNT_TYPE, 187 HFI_PROP_PROFILE, 188 HFI_PROP_LEVEL, 189 HFI_PROP_SIGNAL_COLOR_INFO, 190 }; 191 192 static const u32 sm8550_vdec_output_config_params[] = { 193 HFI_PROP_COLOR_FORMAT, 194 HFI_PROP_LINEAR_STRIDE_SCANLINE, 195 }; 196 197 static const u32 sm8550_vdec_subscribe_input_properties[] = { 198 HFI_PROP_NO_OUTPUT, 199 }; 200 201 static const u32 sm8550_vdec_subscribe_output_properties[] = { 202 HFI_PROP_PICTURE_TYPE, 203 HFI_PROP_CABAC_SESSION, 204 }; 205 206 static const u32 sm8550_dec_ip_int_buf_tbl[] = { 207 BUF_BIN, 208 BUF_COMV, 209 BUF_NON_COMV, 210 BUF_LINE, 211 }; 212 213 static const u32 sm8550_dec_op_int_buf_tbl[] = { 214 BUF_DPB, 215 }; 216 217 struct iris_platform_data sm8550_data = { 218 .get_instance = iris_hfi_gen2_get_instance, 219 .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, 220 .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, 221 .vpu_ops = &iris_vpu3_ops, 222 .set_preset_registers = iris_set_sm8550_preset_registers, 223 .icc_tbl = sm8550_icc_table, 224 .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), 225 .clk_rst_tbl = sm8550_clk_reset_table, 226 .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), 227 .bw_tbl_dec = sm8550_bw_table_dec, 228 .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), 229 .pmdomain_tbl = sm8550_pmdomain_table, 230 .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), 231 .opp_pd_tbl = sm8550_opp_pd_table, 232 .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), 233 .clk_tbl = sm8550_clk_table, 234 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), 235 /* Upper bound of DMA address range */ 236 .dma_mask = 0xe0000000 - 1, 237 .fwname = "qcom/vpu/vpu30_p4.mbn", 238 .pas_id = IRIS_PAS_ID, 239 .inst_caps = &platform_inst_cap_sm8550, 240 .inst_fw_caps = inst_fw_cap_sm8550, 241 .inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_sm8550), 242 .tz_cp_config_data = &tz_cp_config_sm8550, 243 .core_arch = VIDEO_ARCH_LX, 244 .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, 245 .ubwc_config = &ubwc_config_sm8550, 246 .num_vpp_pipe = 4, 247 .max_session_count = 16, 248 .max_core_mbpf = ((8192 * 4352) / 256) * 2, 249 .input_config_params = 250 sm8550_vdec_input_config_params, 251 .input_config_params_size = 252 ARRAY_SIZE(sm8550_vdec_input_config_params), 253 .output_config_params = 254 sm8550_vdec_output_config_params, 255 .output_config_params_size = 256 ARRAY_SIZE(sm8550_vdec_output_config_params), 257 .dec_input_prop = sm8550_vdec_subscribe_input_properties, 258 .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), 259 .dec_output_prop = sm8550_vdec_subscribe_output_properties, 260 .dec_output_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_output_properties), 261 262 .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, 263 .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), 264 .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, 265 .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), 266 }; 267