| bd870cfd | 16-Jul-2024 |
Nicholas Kazlauskas <[email protected]> |
drm/amd/display: Add seamless boot support for more DIG operation modes
[Why] When pre-OS firmware enables display support for displays that operate the DIG in 2 pixels per cycle processing modes th
drm/amd/display: Add seamless boot support for more DIG operation modes
[Why] When pre-OS firmware enables display support for displays that operate the DIG in 2 pixels per cycle processing modes the inferred pixel rate from get_pixel_clk_frequency_100hz does not account for the true pixel rate since we're outputting 2 per cycle past the stream encoder.
This causes seamless boot validation to abort early.
[How] Add a new stream encoder function for getting pixels per cycle from the stream encoder. If the pixels per cycle is greater than 1 and the driver policy is to enable 2 pixels per cycle for post-OS then allow seamless boot to continue.
Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
show more ...
|