1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 27 static const guid_t MCE = CPER_NOTIFY_MCE; 28 static const guid_t CMC = CPER_NOTIFY_CMC; 29 static const guid_t BOOT = BOOT_TYPE; 30 31 static const guid_t CRASHDUMP = AMD_CRASHDUMP; 32 static const guid_t RUNTIME = AMD_GPU_NONSTANDARD_ERROR; 33 34 static void __inc_entry_length(struct cper_hdr *hdr, uint32_t size) 35 { 36 hdr->record_length += size; 37 } 38 39 static void amdgpu_cper_get_timestamp(struct cper_timestamp *timestamp) 40 { 41 struct tm tm; 42 time64_t now = ktime_get_real_seconds(); 43 44 time64_to_tm(now, 0, &tm); 45 timestamp->seconds = tm.tm_sec; 46 timestamp->minutes = tm.tm_min; 47 timestamp->hours = tm.tm_hour; 48 timestamp->flag = 0; 49 timestamp->day = tm.tm_mday; 50 timestamp->month = 1 + tm.tm_mon; 51 timestamp->year = (1900 + tm.tm_year) % 100; 52 timestamp->century = (1900 + tm.tm_year) / 100; 53 } 54 55 void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev, 56 struct cper_hdr *hdr, 57 enum amdgpu_cper_type type, 58 enum cper_error_severity sev) 59 { 60 hdr->signature[0] = 'C'; 61 hdr->signature[1] = 'P'; 62 hdr->signature[2] = 'E'; 63 hdr->signature[3] = 'R'; 64 hdr->revision = CPER_HDR_REV_1; 65 hdr->signature_end = 0xFFFFFFFF; 66 hdr->error_severity = sev; 67 68 hdr->valid_bits.platform_id = 1; 69 hdr->valid_bits.partition_id = 1; 70 hdr->valid_bits.timestamp = 1; 71 72 amdgpu_cper_get_timestamp(&hdr->timestamp); 73 74 snprintf(hdr->record_id, 8, "%d", atomic_inc_return(&adev->cper.unique_id)); 75 snprintf(hdr->platform_id, 16, "0x%04X:0x%04X", 76 adev->pdev->vendor, adev->pdev->device); 77 /* pmfw version should be part of creator_id according to CPER spec */ 78 snprintf(hdr->creator_id, 16, "%s", CPER_CREATOR_ID_AMDGPU); 79 80 switch (type) { 81 case AMDGPU_CPER_TYPE_BOOT: 82 hdr->notify_type = BOOT; 83 break; 84 case AMDGPU_CPER_TYPE_FATAL: 85 case AMDGPU_CPER_TYPE_BP_THRESHOLD: 86 hdr->notify_type = MCE; 87 break; 88 case AMDGPU_CPER_TYPE_RUNTIME: 89 if (sev == CPER_SEV_NON_FATAL_CORRECTED) 90 hdr->notify_type = CMC; 91 else 92 hdr->notify_type = MCE; 93 break; 94 default: 95 dev_err(adev->dev, "Unknown CPER Type\n"); 96 break; 97 } 98 99 __inc_entry_length(hdr, HDR_LEN); 100 } 101 102 static int amdgpu_cper_entry_fill_section_desc(struct amdgpu_device *adev, 103 struct cper_sec_desc *section_desc, 104 bool bp_threshold, 105 bool poison, 106 enum cper_error_severity sev, 107 guid_t sec_type, 108 uint32_t section_length, 109 uint32_t section_offset) 110 { 111 section_desc->revision_minor = CPER_SEC_MINOR_REV_1; 112 section_desc->revision_major = CPER_SEC_MAJOR_REV_22; 113 section_desc->sec_offset = section_offset; 114 section_desc->sec_length = section_length; 115 section_desc->valid_bits.fru_text = 1; 116 section_desc->flag_bits.primary = 1; 117 section_desc->severity = sev; 118 section_desc->sec_type = sec_type; 119 120 if (adev->smuio.funcs && 121 adev->smuio.funcs->get_socket_id) 122 snprintf(section_desc->fru_text, 20, "OAM%d", 123 adev->smuio.funcs->get_socket_id(adev)); 124 125 if (bp_threshold) 126 section_desc->flag_bits.exceed_err_threshold = 1; 127 if (poison) 128 section_desc->flag_bits.latent_err = 1; 129 130 return 0; 131 } 132 133 int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev, 134 struct cper_hdr *hdr, 135 uint32_t idx, 136 struct cper_sec_crashdump_reg_data reg_data) 137 { 138 struct cper_sec_desc *section_desc; 139 struct cper_sec_crashdump_fatal *section; 140 141 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); 142 section = (struct cper_sec_crashdump_fatal *)((uint8_t *)hdr + 143 FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); 144 145 amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false, 146 CPER_SEV_FATAL, CRASHDUMP, FATAL_SEC_LEN, 147 FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); 148 149 section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH; 150 section->body.reg_arr_size = sizeof(reg_data); 151 section->body.data = reg_data; 152 153 __inc_entry_length(hdr, SEC_DESC_LEN + FATAL_SEC_LEN); 154 155 return 0; 156 } 157 158 int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev, 159 struct cper_hdr *hdr, 160 uint32_t idx, 161 enum cper_error_severity sev, 162 uint32_t *reg_dump, 163 uint32_t reg_count) 164 { 165 struct cper_sec_desc *section_desc; 166 struct cper_sec_nonstd_err *section; 167 bool poison; 168 169 poison = (sev == CPER_SEV_NON_FATAL_CORRECTED) ? false : true; 170 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); 171 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + 172 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 173 174 amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, poison, 175 sev, RUNTIME, NONSTD_SEC_LEN, 176 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 177 178 reg_count = umin(reg_count, CPER_ACA_REG_COUNT); 179 180 section->hdr.valid_bits.err_info_cnt = 1; 181 section->hdr.valid_bits.err_context_cnt = 1; 182 183 section->info.error_type = RUNTIME; 184 section->info.ms_chk_bits.err_type_valid = 1; 185 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; 186 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); 187 188 memcpy(section->ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t)); 189 190 __inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN); 191 192 return 0; 193 } 194 195 int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev, 196 struct cper_hdr *hdr, 197 uint32_t idx) 198 { 199 struct cper_sec_desc *section_desc; 200 struct cper_sec_nonstd_err *section; 201 202 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); 203 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + 204 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 205 206 amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false, 207 CPER_SEV_NUM, RUNTIME, NONSTD_SEC_LEN, 208 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 209 210 section->hdr.valid_bits.err_info_cnt = 1; 211 section->hdr.valid_bits.err_context_cnt = 1; 212 213 section->info.error_type = RUNTIME; 214 section->info.ms_chk_bits.err_type_valid = 1; 215 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; 216 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); 217 218 /* Hardcoded Reg dump for bad page threshold CPER */ 219 section->ctx.reg_dump[CPER_ACA_REG_CTL_LO] = 0x1; 220 section->ctx.reg_dump[CPER_ACA_REG_CTL_HI] = 0x0; 221 section->ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137; 222 section->ctx.reg_dump[CPER_ACA_REG_STATUS_HI] = 0xB0000000; 223 section->ctx.reg_dump[CPER_ACA_REG_ADDR_LO] = 0x0; 224 section->ctx.reg_dump[CPER_ACA_REG_ADDR_HI] = 0x0; 225 section->ctx.reg_dump[CPER_ACA_REG_MISC0_LO] = 0x0; 226 section->ctx.reg_dump[CPER_ACA_REG_MISC0_HI] = 0x0; 227 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2; 228 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff; 229 section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = 0x0; 230 section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x96; 231 section->ctx.reg_dump[CPER_ACA_REG_SYND_LO] = 0x0; 232 section->ctx.reg_dump[CPER_ACA_REG_SYND_HI] = 0x0; 233 234 __inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN); 235 236 return 0; 237 } 238 239 struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev, 240 enum amdgpu_cper_type type, 241 uint16_t section_count) 242 { 243 struct cper_hdr *hdr; 244 uint32_t size = 0; 245 246 size += HDR_LEN; 247 size += (SEC_DESC_LEN * section_count); 248 249 switch (type) { 250 case AMDGPU_CPER_TYPE_RUNTIME: 251 case AMDGPU_CPER_TYPE_BP_THRESHOLD: 252 size += (NONSTD_SEC_LEN * section_count); 253 break; 254 case AMDGPU_CPER_TYPE_FATAL: 255 size += (FATAL_SEC_LEN * section_count); 256 break; 257 case AMDGPU_CPER_TYPE_BOOT: 258 size += (BOOT_SEC_LEN * section_count); 259 break; 260 default: 261 dev_err(adev->dev, "Unknown CPER Type!\n"); 262 return NULL; 263 } 264 265 hdr = kzalloc(size, GFP_KERNEL); 266 if (!hdr) 267 return NULL; 268 269 /* Save this early */ 270 hdr->sec_cnt = section_count; 271 272 return hdr; 273 } 274 275 int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev, 276 struct aca_bank *bank) 277 { 278 struct cper_hdr *fatal = NULL; 279 struct cper_sec_crashdump_reg_data reg_data = { 0 }; 280 struct amdgpu_ring *ring = &adev->cper.ring_buf; 281 int ret; 282 283 fatal = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_FATAL, 1); 284 if (!fatal) { 285 dev_err(adev->dev, "fail to alloc cper entry for ue record\n"); 286 return -ENOMEM; 287 } 288 289 reg_data.status_lo = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 290 reg_data.status_hi = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 291 reg_data.addr_lo = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 292 reg_data.addr_hi = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 293 reg_data.ipid_lo = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); 294 reg_data.ipid_hi = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]); 295 reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); 296 reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); 297 298 amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL); 299 ret = amdgpu_cper_entry_fill_fatal_section(adev, fatal, 0, reg_data); 300 if (ret) 301 return ret; 302 303 amdgpu_cper_ring_write(ring, fatal, fatal->record_length); 304 kfree(fatal); 305 306 return 0; 307 } 308 309 int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev) 310 { 311 struct cper_hdr *bp_threshold = NULL; 312 struct amdgpu_ring *ring = &adev->cper.ring_buf; 313 int ret; 314 315 bp_threshold = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_BP_THRESHOLD, 1); 316 if (!bp_threshold) { 317 dev_err(adev->dev, "fail to alloc cper entry for bad page threshold record\n"); 318 return -ENOMEM; 319 } 320 321 amdgpu_cper_entry_fill_hdr(adev, bp_threshold, AMDGPU_CPER_TYPE_BP_THRESHOLD, CPER_SEV_NUM); 322 ret = amdgpu_cper_entry_fill_bad_page_threshold_section(adev, bp_threshold, 0); 323 if (ret) 324 return ret; 325 326 amdgpu_cper_ring_write(ring, bp_threshold, bp_threshold->record_length); 327 kfree(bp_threshold); 328 329 return 0; 330 } 331 332 static enum cper_error_severity amdgpu_aca_err_type_to_cper_sev(struct amdgpu_device *adev, 333 enum aca_error_type aca_err_type) 334 { 335 switch (aca_err_type) { 336 case ACA_ERROR_TYPE_UE: 337 return CPER_SEV_FATAL; 338 case ACA_ERROR_TYPE_CE: 339 return CPER_SEV_NON_FATAL_CORRECTED; 340 case ACA_ERROR_TYPE_DEFERRED: 341 return CPER_SEV_NON_FATAL_UNCORRECTED; 342 default: 343 dev_err(adev->dev, "Unknown ACA error type!\n"); 344 return CPER_SEV_FATAL; 345 } 346 } 347 348 int amdgpu_cper_generate_ce_records(struct amdgpu_device *adev, 349 struct aca_banks *banks, 350 uint16_t bank_count) 351 { 352 struct cper_hdr *corrected = NULL; 353 enum cper_error_severity sev = CPER_SEV_NON_FATAL_CORRECTED; 354 struct amdgpu_ring *ring = &adev->cper.ring_buf; 355 uint32_t reg_data[CPER_ACA_REG_COUNT] = { 0 }; 356 struct aca_bank_node *node; 357 struct aca_bank *bank; 358 uint32_t i = 0; 359 int ret; 360 361 corrected = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_RUNTIME, bank_count); 362 if (!corrected) { 363 dev_err(adev->dev, "fail to allocate cper entry for ce records\n"); 364 return -ENOMEM; 365 } 366 367 /* Raise severity if any DE is detected in the ACA bank list */ 368 list_for_each_entry(node, &banks->list, node) { 369 bank = &node->bank; 370 if (bank->aca_err_type == ACA_ERROR_TYPE_DEFERRED) { 371 sev = CPER_SEV_NON_FATAL_UNCORRECTED; 372 break; 373 } 374 } 375 376 amdgpu_cper_entry_fill_hdr(adev, corrected, AMDGPU_CPER_TYPE_RUNTIME, sev); 377 378 /* Combine CE and DE in cper record */ 379 list_for_each_entry(node, &banks->list, node) { 380 bank = &node->bank; 381 reg_data[CPER_ACA_REG_CTL_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CTL]); 382 reg_data[CPER_ACA_REG_CTL_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CTL]); 383 reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 384 reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 385 reg_data[CPER_ACA_REG_ADDR_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 386 reg_data[CPER_ACA_REG_ADDR_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 387 reg_data[CPER_ACA_REG_MISC0_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_MISC0]); 388 reg_data[CPER_ACA_REG_MISC0_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_MISC0]); 389 reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); 390 reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); 391 reg_data[CPER_ACA_REG_IPID_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); 392 reg_data[CPER_ACA_REG_IPID_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]); 393 reg_data[CPER_ACA_REG_SYND_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); 394 reg_data[CPER_ACA_REG_SYND_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); 395 396 ret = amdgpu_cper_entry_fill_runtime_section(adev, corrected, i++, 397 amdgpu_aca_err_type_to_cper_sev(adev, bank->aca_err_type), 398 reg_data, CPER_ACA_REG_COUNT); 399 if (ret) 400 return ret; 401 } 402 403 amdgpu_cper_ring_write(ring, corrected, corrected->record_length); 404 kfree(corrected); 405 406 return 0; 407 } 408 409 static bool amdgpu_cper_is_hdr(struct amdgpu_ring *ring, u64 pos) 410 { 411 struct cper_hdr *chdr; 412 413 chdr = (struct cper_hdr *)&(ring->ring[pos]); 414 return strcmp(chdr->signature, "CPER") ? false : true; 415 } 416 417 static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos) 418 { 419 struct cper_hdr *chdr; 420 u64 p; 421 u32 chunk, rec_len = 0; 422 423 chdr = (struct cper_hdr *)&(ring->ring[pos]); 424 chunk = ring->ring_size - (pos << 2); 425 426 if (!strcmp(chdr->signature, "CPER")) { 427 rec_len = chdr->record_length; 428 goto calc; 429 } 430 431 /* ring buffer is not full, no cper data after ring->wptr */ 432 if (ring->count_dw) 433 goto calc; 434 435 for (p = pos + 1; p <= ring->buf_mask; p++) { 436 chdr = (struct cper_hdr *)&(ring->ring[p]); 437 if (!strcmp(chdr->signature, "CPER")) { 438 rec_len = (p - pos) << 2; 439 goto calc; 440 } 441 } 442 443 calc: 444 if (!rec_len) 445 return chunk; 446 else 447 return umin(rec_len, chunk); 448 } 449 450 void amdgpu_cper_ring_write(struct amdgpu_ring *ring, 451 void *src, int count) 452 { 453 u64 pos, wptr_old, rptr = *ring->rptr_cpu_addr & ring->ptr_mask; 454 u32 chunk, ent_sz; 455 u8 *s = (u8 *)src; 456 457 if (count >= ring->ring_size - 4) { 458 dev_err(ring->adev->dev, 459 "CPER data size(%d) is larger than ring size(%d)\n", 460 count, ring->ring_size - 4); 461 462 return; 463 } 464 465 wptr_old = ring->wptr; 466 467 mutex_lock(&ring->adev->cper.ring_lock); 468 while (count) { 469 ent_sz = amdgpu_cper_ring_get_ent_sz(ring, ring->wptr); 470 chunk = umin(ent_sz, count); 471 472 memcpy(&ring->ring[ring->wptr], s, chunk); 473 474 ring->wptr += (chunk >> 2); 475 ring->wptr &= ring->ptr_mask; 476 count -= chunk; 477 s += chunk; 478 } 479 480 /* the buffer is overflow, adjust rptr */ 481 if (((wptr_old < rptr) && (rptr <= ring->wptr)) || 482 ((ring->wptr < wptr_old) && (wptr_old < rptr)) || 483 ((rptr <= ring->wptr) && (ring->wptr < wptr_old))) { 484 pos = (ring->wptr + 1) & ring->ptr_mask; 485 486 do { 487 ent_sz = amdgpu_cper_ring_get_ent_sz(ring, pos); 488 489 rptr += (ent_sz >> 2); 490 rptr &= ring->ptr_mask; 491 *ring->rptr_cpu_addr = rptr; 492 493 pos = rptr; 494 } while (!amdgpu_cper_is_hdr(ring, rptr)); 495 } 496 mutex_unlock(&ring->adev->cper.ring_lock); 497 498 if (ring->count_dw >= (count >> 2)) 499 ring->count_dw -= (count >> 2); 500 else 501 ring->count_dw = 0; 502 } 503 504 static u64 amdgpu_cper_ring_get_rptr(struct amdgpu_ring *ring) 505 { 506 return *(ring->rptr_cpu_addr); 507 } 508 509 static u64 amdgpu_cper_ring_get_wptr(struct amdgpu_ring *ring) 510 { 511 return ring->wptr; 512 } 513 514 static const struct amdgpu_ring_funcs cper_ring_funcs = { 515 .type = AMDGPU_RING_TYPE_CPER, 516 .align_mask = 0xff, 517 .support_64bit_ptrs = false, 518 .get_rptr = amdgpu_cper_ring_get_rptr, 519 .get_wptr = amdgpu_cper_ring_get_wptr, 520 }; 521 522 static int amdgpu_cper_ring_init(struct amdgpu_device *adev) 523 { 524 struct amdgpu_ring *ring = &(adev->cper.ring_buf); 525 526 mutex_init(&adev->cper.ring_lock); 527 528 ring->adev = NULL; 529 ring->ring_obj = NULL; 530 ring->use_doorbell = false; 531 ring->no_scheduler = true; 532 ring->funcs = &cper_ring_funcs; 533 534 sprintf(ring->name, "cper"); 535 return amdgpu_ring_init(adev, ring, CPER_MAX_RING_SIZE, NULL, 0, 536 AMDGPU_RING_PRIO_DEFAULT, NULL); 537 } 538 539 int amdgpu_cper_init(struct amdgpu_device *adev) 540 { 541 int r; 542 543 if (!amdgpu_aca_is_enabled(adev)) 544 return 0; 545 546 r = amdgpu_cper_ring_init(adev); 547 if (r) { 548 dev_err(adev->dev, "failed to initialize cper ring, r = %d\n", r); 549 return r; 550 } 551 552 mutex_init(&adev->cper.cper_lock); 553 554 adev->cper.enabled = true; 555 adev->cper.max_count = CPER_MAX_ALLOWED_COUNT; 556 557 return 0; 558 } 559 560 int amdgpu_cper_fini(struct amdgpu_device *adev) 561 { 562 if (!amdgpu_aca_is_enabled(adev)) 563 return 0; 564 565 adev->cper.enabled = false; 566 567 amdgpu_ring_fini(&(adev->cper.ring_buf)); 568 adev->cper.count = 0; 569 adev->cper.wptr = 0; 570 571 return 0; 572 } 573