1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file implements the WebAssemblyTargetLowering class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "wasm-lower"
39 
40 namespace {
41 // Diagnostic information for unimplemented or unsupported feature reporting.
42 // FIXME copied from BPF and AMDGPU.
43 class DiagnosticInfoUnsupported : public DiagnosticInfo {
44 private:
45   // Debug location where this diagnostic is triggered.
46   DebugLoc DLoc;
47   const Twine &Description;
48   const Function &Fn;
49   SDValue Value;
50 
51   static int KindID;
52 
53   static int getKindID() {
54     if (KindID == 0)
55       KindID = llvm::getNextAvailablePluginDiagnosticKind();
56     return KindID;
57   }
58 
59 public:
60   DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
61                             SDValue Value)
62       : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
63         Description(Desc), Fn(Fn), Value(Value) {}
64 
65   void print(DiagnosticPrinter &DP) const override {
66     std::string Str;
67     raw_string_ostream OS(Str);
68 
69     if (DLoc) {
70       auto DIL = DLoc.get();
71       StringRef Filename = DIL->getFilename();
72       unsigned Line = DIL->getLine();
73       unsigned Column = DIL->getColumn();
74       OS << Filename << ':' << Line << ':' << Column << ' ';
75     }
76 
77     OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
78        << Description;
79     if (Value)
80       Value->print(OS);
81     OS << '\n';
82     OS.flush();
83     DP << Str;
84   }
85 
86   static bool classof(const DiagnosticInfo *DI) {
87     return DI->getKind() == getKindID();
88   }
89 };
90 
91 int DiagnosticInfoUnsupported::KindID = 0;
92 } // end anonymous namespace
93 
94 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
95     const TargetMachine &TM, const WebAssemblySubtarget &STI)
96     : TargetLowering(TM), Subtarget(&STI) {
97   auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
98 
99   // Booleans always contain 0 or 1.
100   setBooleanContents(ZeroOrOneBooleanContent);
101   // WebAssembly does not produce floating-point exceptions on normal floating
102   // point operations.
103   setHasFloatingPointExceptions(false);
104   // We don't know the microarchitecture here, so just reduce register pressure.
105   setSchedulingPreference(Sched::RegPressure);
106   // Tell ISel that we have a stack pointer.
107   setStackPointerRegisterToSaveRestore(
108       Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
109   // Set up the register classes.
110   addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
111   addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
112   addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
113   addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
114   // Compute derived properties from the register classes.
115   computeRegisterProperties(Subtarget->getRegisterInfo());
116 
117   setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
118   setOperationAction(ISD::JumpTable, MVTPtr, Custom);
119 
120   for (auto T : {MVT::f32, MVT::f64}) {
121     // Don't expand the floating-point types to constant pools.
122     setOperationAction(ISD::ConstantFP, T, Legal);
123     // Expand floating-point comparisons.
124     for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
125                     ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
126       setCondCodeAction(CC, T, Expand);
127     // Expand floating-point library function operators.
128     for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW})
129       setOperationAction(Op, T, Expand);
130     // Note supported floating-point library function operators that otherwise
131     // default to expand.
132     for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
133                     ISD::FRINT})
134       setOperationAction(Op, T, Legal);
135     // Support minnan and maxnan, which otherwise default to expand.
136     setOperationAction(ISD::FMINNAN, T, Legal);
137     setOperationAction(ISD::FMAXNAN, T, Legal);
138   }
139 
140   for (auto T : {MVT::i32, MVT::i64}) {
141     // Expand unavailable integer operations.
142     for (auto Op : {ISD::BSWAP, ISD::ROTL, ISD::ROTR,
143                     ISD::SMUL_LOHI, ISD::UMUL_LOHI,
144                     ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM,
145                     ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
146                     ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
147       setOperationAction(Op, T, Expand);
148     }
149   }
150 
151   // As a special case, these operators use the type to mean the type to
152   // sign-extend from.
153   for (auto T : {MVT::i1, MVT::i8, MVT::i16})
154     setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
155 
156   // Dynamic stack allocation: use the default expansion.
157   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
158   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
159   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
160 
161   // Expand these forms; we pattern-match the forms that we can handle in isel.
162   for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
163     for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
164       setOperationAction(Op, T, Expand);
165 
166   // We have custom switch handling.
167   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
168 
169   // WebAssembly doesn't have:
170   //  - Floating-point extending loads.
171   //  - Floating-point truncating stores.
172   //  - i1 extending loads.
173   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f64, Expand);
174   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
175   for (auto T : MVT::integer_valuetypes())
176     for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
177       setLoadExtAction(Ext, T, MVT::i1, Promote);
178 
179   // Trap lowers to wasm unreachable
180   setOperationAction(ISD::TRAP, MVT::Other, Legal);
181 }
182 
183 FastISel *WebAssemblyTargetLowering::createFastISel(
184     FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
185   return WebAssembly::createFastISel(FuncInfo, LibInfo);
186 }
187 
188 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
189     const GlobalAddressSDNode *GA) const {
190   // The WebAssembly target doesn't support folding offsets into global
191   // addresses.
192   return false;
193 }
194 
195 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
196                                                       EVT VT) const {
197   return VT.getSimpleVT();
198 }
199 
200 const char *
201 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
202   switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
203   case WebAssemblyISD::FIRST_NUMBER:
204     break;
205 #define HANDLE_NODETYPE(NODE)                                                  \
206   case WebAssemblyISD::NODE:                                                   \
207     return "WebAssemblyISD::" #NODE;
208 #include "WebAssemblyISD.def"
209 #undef HANDLE_NODETYPE
210   }
211   return nullptr;
212 }
213 
214 std::pair<unsigned, const TargetRegisterClass *>
215 WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
216     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
217   // First, see if this is a constraint that directly corresponds to a
218   // WebAssembly register class.
219   if (Constraint.size() == 1) {
220     switch (Constraint[0]) {
221     case 'r':
222       return std::make_pair(0U, &WebAssembly::I32RegClass);
223     default:
224       break;
225     }
226   }
227 
228   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
229 }
230 
231 //===----------------------------------------------------------------------===//
232 // WebAssembly Lowering private implementation.
233 //===----------------------------------------------------------------------===//
234 
235 //===----------------------------------------------------------------------===//
236 // Lowering Code
237 //===----------------------------------------------------------------------===//
238 
239 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
240   MachineFunction &MF = DAG.getMachineFunction();
241   DAG.getContext()->diagnose(
242       DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
243 }
244 
245 SDValue
246 WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
247                                      SmallVectorImpl<SDValue> &InVals) const {
248   SelectionDAG &DAG = CLI.DAG;
249   SDLoc DL = CLI.DL;
250   SDValue Chain = CLI.Chain;
251   SDValue Callee = CLI.Callee;
252   MachineFunction &MF = DAG.getMachineFunction();
253 
254   CallingConv::ID CallConv = CLI.CallConv;
255   if (CallConv != CallingConv::C &&
256       CallConv != CallingConv::Fast &&
257       CallConv != CallingConv::Cold)
258     fail(DL, DAG,
259          "WebAssembly doesn't support language-specific or target-specific "
260          "calling conventions yet");
261   if (CLI.IsPatchPoint)
262     fail(DL, DAG, "WebAssembly doesn't support patch point yet");
263 
264   // WebAssembly doesn't currently support explicit tail calls. If they are
265   // required, fail. Otherwise, just disable them.
266   if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
267        MF.getTarget().Options.GuaranteedTailCallOpt) ||
268       (CLI.CS && CLI.CS->isMustTailCall()))
269     fail(DL, DAG, "WebAssembly doesn't support tail call yet");
270   CLI.IsTailCall = false;
271 
272   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
273 
274   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
275   if (Ins.size() > 1)
276     fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
277 
278   bool IsVarArg = CLI.IsVarArg;
279   if (IsVarArg)
280     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
281 
282   // Analyze operands of the call, assigning locations to each operand.
283   SmallVector<CCValAssign, 16> ArgLocs;
284   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
285   unsigned NumBytes = CCInfo.getNextStackOffset();
286 
287   auto PtrVT = getPointerTy(MF.getDataLayout());
288   auto Zero = DAG.getConstant(0, DL, PtrVT, true);
289   auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
290   Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
291 
292   SmallVector<SDValue, 16> Ops;
293   Ops.push_back(Chain);
294   Ops.push_back(Callee);
295   Ops.append(OutVals.begin(), OutVals.end());
296 
297   SmallVector<EVT, 8> Tys;
298   for (const auto &In : Ins)
299     Tys.push_back(In.VT);
300   Tys.push_back(MVT::Other);
301   SDVTList TyList = DAG.getVTList(Tys);
302   SDValue Res =
303       DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
304                   DL, TyList, Ops);
305   if (Ins.empty()) {
306     Chain = Res;
307   } else {
308     InVals.push_back(Res);
309     Chain = Res.getValue(1);
310   }
311 
312   Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
313 
314   return Chain;
315 }
316 
317 bool WebAssemblyTargetLowering::CanLowerReturn(
318     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
319     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
320   // WebAssembly can't currently handle returning tuples.
321   return Outs.size() <= 1;
322 }
323 
324 SDValue WebAssemblyTargetLowering::LowerReturn(
325     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
326     const SmallVectorImpl<ISD::OutputArg> &Outs,
327     const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
328     SelectionDAG &DAG) const {
329   assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
330   if (CallConv != CallingConv::C)
331     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
332   if (IsVarArg)
333     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
334 
335   SmallVector<SDValue, 4> RetOps(1, Chain);
336   RetOps.append(OutVals.begin(), OutVals.end());
337   Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
338 
339   // Record the number and types of the return values.
340   for (const ISD::OutputArg &Out : Outs) {
341     if (Out.Flags.isByVal())
342       fail(DL, DAG, "WebAssembly hasn't implemented byval results");
343     if (Out.Flags.isInAlloca())
344       fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
345     if (Out.Flags.isNest())
346       fail(DL, DAG, "WebAssembly hasn't implemented nest results");
347     if (Out.Flags.isInConsecutiveRegs())
348       fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
349     if (Out.Flags.isInConsecutiveRegsLast())
350       fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
351     if (!Out.IsFixed)
352       fail(DL, DAG, "WebAssembly doesn't support non-fixed results yet");
353   }
354 
355   return Chain;
356 }
357 
358 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
359     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
360     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
361     SmallVectorImpl<SDValue> &InVals) const {
362   MachineFunction &MF = DAG.getMachineFunction();
363 
364   if (CallConv != CallingConv::C)
365     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
366   if (IsVarArg)
367     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
368 
369   for (const ISD::InputArg &In : Ins) {
370     if (In.Flags.isByVal())
371       fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
372     if (In.Flags.isInAlloca())
373       fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
374     if (In.Flags.isNest())
375       fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
376     if (In.Flags.isInConsecutiveRegs())
377       fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
378     if (In.Flags.isInConsecutiveRegsLast())
379       fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
380     // FIXME Do something with In.getOrigAlign()?
381     InVals.push_back(
382         In.Used
383             ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
384                           DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
385             : DAG.getNode(ISD::UNDEF, DL, In.VT));
386 
387     // Record the number and types of arguments.
388     MF.getInfo<WebAssemblyFunctionInfo>()->addParam(In.VT);
389   }
390 
391   return Chain;
392 }
393 
394 //===----------------------------------------------------------------------===//
395 //  Custom lowering hooks.
396 //===----------------------------------------------------------------------===//
397 
398 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
399                                                   SelectionDAG &DAG) const {
400   switch (Op.getOpcode()) {
401   default:
402     llvm_unreachable("unimplemented operation lowering");
403     return SDValue();
404   case ISD::GlobalAddress:
405     return LowerGlobalAddress(Op, DAG);
406   case ISD::JumpTable:
407     return LowerJumpTable(Op, DAG);
408   case ISD::BR_JT:
409     return LowerBR_JT(Op, DAG);
410   }
411 }
412 
413 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
414                                                       SelectionDAG &DAG) const {
415   SDLoc DL(Op);
416   const auto *GA = cast<GlobalAddressSDNode>(Op);
417   EVT VT = Op.getValueType();
418   assert(GA->getOffset() == 0 &&
419          "offsets on global addresses are forbidden by isOffsetFoldingLegal");
420   assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
421   if (GA->getAddressSpace() != 0)
422     fail(DL, DAG, "WebAssembly only expects the 0 address space");
423   return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
424                      DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
425 }
426 
427 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
428                                                   SelectionDAG &DAG) const {
429   // There's no need for a Wrapper node because we always incorporate a jump
430   // table operand into a SWITCH instruction, rather than ever materializing
431   // it in a register.
432   const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
433   return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
434                                 JT->getTargetFlags());
435 }
436 
437 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
438                                               SelectionDAG &DAG) const {
439   SDLoc DL(Op);
440   SDValue Chain = Op.getOperand(0);
441   const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
442   SDValue Index = Op.getOperand(2);
443   assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
444 
445   SmallVector<SDValue, 8> Ops;
446   Ops.push_back(Chain);
447   Ops.push_back(Index);
448 
449   MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
450   const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
451 
452   // TODO: For now, we just pick something arbitrary for a default case for now.
453   // We really want to sniff out the guard and put in the real default case (and
454   // delete the guard).
455   Ops.push_back(DAG.getBasicBlock(MBBs[0]));
456 
457   // Add an operand for each case.
458   for (auto MBB : MBBs)
459     Ops.push_back(DAG.getBasicBlock(MBB));
460 
461   return DAG.getNode(WebAssemblyISD::SWITCH, DL, MVT::Other, Ops);
462 }
463 
464 //===----------------------------------------------------------------------===//
465 //                          WebAssembly Optimization Hooks
466 //===----------------------------------------------------------------------===//
467 
468 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
469     const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
470     const TargetMachine &TM) const {
471   // TODO: Be more sophisticated than this.
472   return isa<Function>(GV) ? getTextSection() : getDataSection();
473 }
474