1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file implements the WebAssemblyTargetLowering class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "wasm-lower"
39 
40 namespace {
41 // Diagnostic information for unimplemented or unsupported feature reporting.
42 // FIXME copied from BPF and AMDGPU.
43 class DiagnosticInfoUnsupported : public DiagnosticInfo {
44 private:
45   // Debug location where this diagnostic is triggered.
46   DebugLoc DLoc;
47   const Twine &Description;
48   const Function &Fn;
49   SDValue Value;
50 
51   static int KindID;
52 
53   static int getKindID() {
54     if (KindID == 0)
55       KindID = llvm::getNextAvailablePluginDiagnosticKind();
56     return KindID;
57   }
58 
59 public:
60   DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
61                             SDValue Value)
62       : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
63         Description(Desc), Fn(Fn), Value(Value) {}
64 
65   void print(DiagnosticPrinter &DP) const override {
66     std::string Str;
67     raw_string_ostream OS(Str);
68 
69     if (DLoc) {
70       auto DIL = DLoc.get();
71       StringRef Filename = DIL->getFilename();
72       unsigned Line = DIL->getLine();
73       unsigned Column = DIL->getColumn();
74       OS << Filename << ':' << Line << ':' << Column << ' ';
75     }
76 
77     OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
78        << Description;
79     if (Value)
80       Value->print(OS);
81     OS << '\n';
82     OS.flush();
83     DP << Str;
84   }
85 
86   static bool classof(const DiagnosticInfo *DI) {
87     return DI->getKind() == getKindID();
88   }
89 };
90 
91 int DiagnosticInfoUnsupported::KindID = 0;
92 } // end anonymous namespace
93 
94 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
95     const TargetMachine &TM, const WebAssemblySubtarget &STI)
96     : TargetLowering(TM), Subtarget(&STI) {
97   auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
98 
99   // Booleans always contain 0 or 1.
100   setBooleanContents(ZeroOrOneBooleanContent);
101   // WebAssembly does not produce floating-point exceptions on normal floating
102   // point operations.
103   setHasFloatingPointExceptions(false);
104   // We don't know the microarchitecture here, so just reduce register pressure.
105   setSchedulingPreference(Sched::RegPressure);
106   // Tell ISel that we have a stack pointer.
107   setStackPointerRegisterToSaveRestore(
108       Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
109   // Set up the register classes.
110   addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
111   addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
112   addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
113   addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
114   // Compute derived properties from the register classes.
115   computeRegisterProperties(Subtarget->getRegisterInfo());
116 
117   setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
118   setOperationAction(ISD::JumpTable, MVTPtr, Custom);
119 
120   for (auto T : {MVT::f32, MVT::f64}) {
121     // Don't expand the floating-point types to constant pools.
122     setOperationAction(ISD::ConstantFP, T, Legal);
123     // Expand floating-point comparisons.
124     for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
125                     ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
126       setCondCodeAction(CC, T, Expand);
127     // Expand floating-point library function operators.
128     for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW})
129       setOperationAction(Op, T, Expand);
130     // Note supported floating-point library function operators that otherwise
131     // default to expand.
132     for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
133                     ISD::FRINT})
134       setOperationAction(Op, T, Legal);
135   }
136 
137   for (auto T : {MVT::i32, MVT::i64}) {
138     // Expand unavailable integer operations.
139     for (auto Op : {ISD::BSWAP, ISD::ROTL, ISD::ROTR,
140                     ISD::SMUL_LOHI, ISD::UMUL_LOHI,
141                     ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM,
142                     ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
143                     ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
144       setOperationAction(Op, T, Expand);
145     }
146   }
147 
148   // As a special case, these operators use the type to mean the type to
149   // sign-extend from.
150   for (auto T : {MVT::i1, MVT::i8, MVT::i16})
151     setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
152 
153   // Dynamic stack allocation: use the default expansion.
154   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
155   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
156   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
157 
158   // Expand these forms; we pattern-match the forms that we can handle in isel.
159   for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
160     for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
161       setOperationAction(Op, T, Expand);
162 
163   // We have custom switch handling.
164   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
165 
166   // WebAssembly doesn't have:
167   //  - Floating-point extending loads.
168   //  - Floating-point truncating stores.
169   //  - i1 extending loads.
170   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f64, Expand);
171   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
172   for (auto T : MVT::integer_valuetypes())
173     for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
174       setLoadExtAction(Ext, T, MVT::i1, Promote);
175 }
176 
177 FastISel *WebAssemblyTargetLowering::createFastISel(
178     FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
179   return WebAssembly::createFastISel(FuncInfo, LibInfo);
180 }
181 
182 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
183     const GlobalAddressSDNode *GA) const {
184   // The WebAssembly target doesn't support folding offsets into global
185   // addresses.
186   return false;
187 }
188 
189 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
190                                                       EVT VT) const {
191   return VT.getSimpleVT();
192 }
193 
194 const char *
195 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
196   switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
197   case WebAssemblyISD::FIRST_NUMBER:
198     break;
199 #define HANDLE_NODETYPE(NODE)                                                  \
200   case WebAssemblyISD::NODE:                                                   \
201     return "WebAssemblyISD::" #NODE;
202 #include "WebAssemblyISD.def"
203 #undef HANDLE_NODETYPE
204   }
205   return nullptr;
206 }
207 
208 //===----------------------------------------------------------------------===//
209 // WebAssembly Lowering private implementation.
210 //===----------------------------------------------------------------------===//
211 
212 //===----------------------------------------------------------------------===//
213 // Lowering Code
214 //===----------------------------------------------------------------------===//
215 
216 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
217   MachineFunction &MF = DAG.getMachineFunction();
218   DAG.getContext()->diagnose(
219       DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
220 }
221 
222 SDValue
223 WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
224                                      SmallVectorImpl<SDValue> &InVals) const {
225   SelectionDAG &DAG = CLI.DAG;
226   SDLoc DL = CLI.DL;
227   SDValue Chain = CLI.Chain;
228   SDValue Callee = CLI.Callee;
229   MachineFunction &MF = DAG.getMachineFunction();
230 
231   CallingConv::ID CallConv = CLI.CallConv;
232   if (CallConv != CallingConv::C)
233     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
234   if (CLI.IsTailCall || MF.getTarget().Options.GuaranteedTailCallOpt)
235     fail(DL, DAG, "WebAssembly doesn't support tail call yet");
236   if (CLI.IsPatchPoint)
237     fail(DL, DAG, "WebAssembly doesn't support patch point yet");
238 
239   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
240   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
241 
242   bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
243   if (IsStructRet)
244     fail(DL, DAG, "WebAssembly doesn't support struct return yet");
245 
246   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
247   if (Ins.size() > 1)
248     fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
249 
250   bool IsVarArg = CLI.IsVarArg;
251   if (IsVarArg)
252     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
253 
254   // Analyze operands of the call, assigning locations to each operand.
255   SmallVector<CCValAssign, 16> ArgLocs;
256   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
257   unsigned NumBytes = CCInfo.getNextStackOffset();
258 
259   auto PtrVT = getPointerTy(MF.getDataLayout());
260   auto Zero = DAG.getConstant(0, DL, PtrVT, true);
261   auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
262   Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
263 
264   SmallVector<SDValue, 16> Ops;
265   Ops.push_back(Chain);
266   Ops.push_back(Callee);
267   Ops.append(OutVals.begin(), OutVals.end());
268 
269   SmallVector<EVT, 8> Tys;
270   for (const auto &In : Ins)
271     Tys.push_back(In.VT);
272   Tys.push_back(MVT::Other);
273   SDVTList TyList = DAG.getVTList(Tys);
274   SDValue Res =
275       DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
276                   DL, TyList, Ops);
277   if (Ins.empty()) {
278     Chain = Res;
279   } else {
280     InVals.push_back(Res);
281     Chain = Res.getValue(1);
282   }
283 
284   // FIXME: handle CLI.RetSExt and CLI.RetZExt?
285 
286   Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
287 
288   return Chain;
289 }
290 
291 bool WebAssemblyTargetLowering::CanLowerReturn(
292     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
293     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
294   // WebAssembly can't currently handle returning tuples.
295   return Outs.size() <= 1;
296 }
297 
298 SDValue WebAssemblyTargetLowering::LowerReturn(
299     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
300     const SmallVectorImpl<ISD::OutputArg> &Outs,
301     const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
302     SelectionDAG &DAG) const {
303 
304   assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
305   if (CallConv != CallingConv::C)
306     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
307   if (IsVarArg)
308     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
309 
310   SmallVector<SDValue, 4> RetOps(1, Chain);
311   RetOps.append(OutVals.begin(), OutVals.end());
312   Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
313 
314   return Chain;
315 }
316 
317 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
318     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
319     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
320     SmallVectorImpl<SDValue> &InVals) const {
321   MachineFunction &MF = DAG.getMachineFunction();
322 
323   if (CallConv != CallingConv::C)
324     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
325   if (IsVarArg)
326     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
327   if (MF.getFunction()->hasStructRetAttr())
328     fail(DL, DAG, "WebAssembly doesn't support struct return yet");
329 
330   unsigned ArgNo = 0;
331   for (const ISD::InputArg &In : Ins) {
332     if (In.Flags.isZExt())
333       fail(DL, DAG, "WebAssembly hasn't implemented zext arguments");
334     if (In.Flags.isSExt())
335       fail(DL, DAG, "WebAssembly hasn't implemented sext arguments");
336     if (In.Flags.isInReg())
337       fail(DL, DAG, "WebAssembly hasn't implemented inreg arguments");
338     if (In.Flags.isSRet())
339       fail(DL, DAG, "WebAssembly hasn't implemented sret arguments");
340     if (In.Flags.isByVal())
341       fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
342     if (In.Flags.isInAlloca())
343       fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
344     if (In.Flags.isNest())
345       fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
346     if (In.Flags.isReturned())
347       fail(DL, DAG, "WebAssembly hasn't implemented returned arguments");
348     if (In.Flags.isInConsecutiveRegs())
349       fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
350     if (In.Flags.isInConsecutiveRegsLast())
351       fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
352     if (In.Flags.isSplit())
353       fail(DL, DAG, "WebAssembly hasn't implemented split arguments");
354     // FIXME Do something with In.getOrigAlign()?
355     InVals.push_back(
356         In.Used
357             ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
358                           DAG.getTargetConstant(ArgNo, DL, MVT::i32))
359             : DAG.getNode(ISD::UNDEF, DL, In.VT));
360     ++ArgNo;
361   }
362 
363   return Chain;
364 }
365 
366 //===----------------------------------------------------------------------===//
367 //  Custom lowering hooks.
368 //===----------------------------------------------------------------------===//
369 
370 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
371                                                   SelectionDAG &DAG) const {
372   switch (Op.getOpcode()) {
373   default:
374     llvm_unreachable("unimplemented operation lowering");
375     return SDValue();
376   case ISD::GlobalAddress:
377     return LowerGlobalAddress(Op, DAG);
378   case ISD::JumpTable:
379     return LowerJumpTable(Op, DAG);
380   case ISD::BR_JT:
381     return LowerBR_JT(Op, DAG);
382   }
383 }
384 
385 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
386                                                       SelectionDAG &DAG) const {
387   SDLoc DL(Op);
388   const auto *GA = cast<GlobalAddressSDNode>(Op);
389   EVT VT = Op.getValueType();
390   assert(GA->getOffset() == 0 &&
391          "offsets on global addresses are forbidden by isOffsetFoldingLegal");
392   assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
393   if (GA->getAddressSpace() != 0)
394     fail(DL, DAG, "WebAssembly only expects the 0 address space");
395   return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
396                      DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
397 }
398 
399 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
400                                                   SelectionDAG &DAG) const {
401   // There's no need for a Wrapper node because we always incorporate a jump
402   // table operand into a SWITCH instruction, rather than ever materializing
403   // it in a register.
404   const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
405   return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
406                                 JT->getTargetFlags());
407 }
408 
409 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
410                                               SelectionDAG &DAG) const {
411   SDLoc DL(Op);
412   SDValue Chain = Op.getOperand(0);
413   const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
414   SDValue Index = Op.getOperand(2);
415   assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
416 
417   SmallVector<SDValue, 8> Ops;
418   Ops.push_back(Chain);
419   Ops.push_back(Index);
420 
421   MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
422   const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
423 
424   // TODO: For now, we just pick something arbitrary for a default case for now.
425   // We really want to sniff out the guard and put in the real default case (and
426   // delete the guard).
427   Ops.push_back(DAG.getBasicBlock(MBBs[0]));
428 
429   // Add an operand for each case.
430   for (auto MBB : MBBs)
431     Ops.push_back(DAG.getBasicBlock(MBB));
432 
433   return DAG.getNode(WebAssemblyISD::SWITCH, DL, MVT::Other, Ops);
434 }
435 
436 //===----------------------------------------------------------------------===//
437 //                          WebAssembly Optimization Hooks
438 //===----------------------------------------------------------------------===//
439 
440 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
441     const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
442     const TargetMachine &TM) const {
443   return getDataSection();
444 }
445