1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file implements the WebAssemblyTargetLowering class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "wasm-lower"
39 
40 namespace {
41 // Diagnostic information for unimplemented or unsupported feature reporting.
42 // FIXME copied from BPF and AMDGPU.
43 class DiagnosticInfoUnsupported : public DiagnosticInfo {
44 private:
45   // Debug location where this diagnostic is triggered.
46   DebugLoc DLoc;
47   const Twine &Description;
48   const Function &Fn;
49   SDValue Value;
50 
51   static int KindID;
52 
53   static int getKindID() {
54     if (KindID == 0)
55       KindID = llvm::getNextAvailablePluginDiagnosticKind();
56     return KindID;
57   }
58 
59 public:
60   DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
61                             SDValue Value)
62       : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
63         Description(Desc), Fn(Fn), Value(Value) {}
64 
65   void print(DiagnosticPrinter &DP) const override {
66     std::string Str;
67     raw_string_ostream OS(Str);
68 
69     if (DLoc) {
70       auto DIL = DLoc.get();
71       StringRef Filename = DIL->getFilename();
72       unsigned Line = DIL->getLine();
73       unsigned Column = DIL->getColumn();
74       OS << Filename << ':' << Line << ':' << Column << ' ';
75     }
76 
77     OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
78        << Description;
79     if (Value)
80       Value->print(OS);
81     OS << '\n';
82     OS.flush();
83     DP << Str;
84   }
85 
86   static bool classof(const DiagnosticInfo *DI) {
87     return DI->getKind() == getKindID();
88   }
89 };
90 
91 int DiagnosticInfoUnsupported::KindID = 0;
92 } // end anonymous namespace
93 
94 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
95     const TargetMachine &TM, const WebAssemblySubtarget &STI)
96     : TargetLowering(TM), Subtarget(&STI) {
97   auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
98 
99   // Booleans always contain 0 or 1.
100   setBooleanContents(ZeroOrOneBooleanContent);
101   // WebAssembly does not produce floating-point exceptions on normal floating
102   // point operations.
103   setHasFloatingPointExceptions(false);
104   // We don't know the microarchitecture here, so just reduce register pressure.
105   setSchedulingPreference(Sched::RegPressure);
106   // Tell ISel that we have a stack pointer.
107   setStackPointerRegisterToSaveRestore(
108       Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
109   // Set up the register classes.
110   addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
111   addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
112   addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
113   addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
114   // Compute derived properties from the register classes.
115   computeRegisterProperties(Subtarget->getRegisterInfo());
116 
117   setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
118   setOperationAction(ISD::JumpTable, MVTPtr, Custom);
119 
120   for (auto T : {MVT::f32, MVT::f64}) {
121     // Don't expand the floating-point types to constant pools.
122     setOperationAction(ISD::ConstantFP, T, Legal);
123     // Expand floating-point comparisons.
124     for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
125                     ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
126       setCondCodeAction(CC, T, Expand);
127     // Expand floating-point library function operators.
128     for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW})
129       setOperationAction(Op, T, Expand);
130     // Note supported floating-point library function operators that otherwise
131     // default to expand.
132     for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
133                     ISD::FRINT})
134       setOperationAction(Op, T, Legal);
135   }
136 
137   for (auto T : {MVT::i32, MVT::i64}) {
138     // Expand unavailable integer operations.
139     for (auto Op : {ISD::BSWAP, ISD::ROTL, ISD::ROTR,
140                     ISD::SMUL_LOHI, ISD::UMUL_LOHI,
141                     ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM,
142                     ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
143                     ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
144       setOperationAction(Op, T, Expand);
145     }
146   }
147 
148   // As a special case, these operators use the type to mean the type to
149   // sign-extend from.
150   for (auto T : {MVT::i1, MVT::i8, MVT::i16})
151     setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
152 
153   // Dynamic stack allocation: use the default expansion.
154   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
155   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
156   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
157 
158   // Expand these forms; we pattern-match the forms that we can handle in isel.
159   for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
160     for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
161       setOperationAction(Op, T, Expand);
162 
163   // We have custom switch handling.
164   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
165 
166   // WebAssembly doesn't have:
167   //  - Floating-point extending loads.
168   //  - Floating-point truncating stores.
169   //  - i1 extending loads.
170   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f64, Expand);
171   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
172   for (auto T : MVT::integer_valuetypes())
173     for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
174       setLoadExtAction(Ext, T, MVT::i1, Promote);
175 }
176 
177 FastISel *WebAssemblyTargetLowering::createFastISel(
178     FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
179   return WebAssembly::createFastISel(FuncInfo, LibInfo);
180 }
181 
182 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
183     const GlobalAddressSDNode *GA) const {
184   // The WebAssembly target doesn't support folding offsets into global
185   // addresses.
186   return false;
187 }
188 
189 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
190                                                       EVT VT) const {
191   return VT.getSimpleVT();
192 }
193 
194 const char *
195 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
196   switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
197   case WebAssemblyISD::FIRST_NUMBER:
198     break;
199 #define HANDLE_NODETYPE(NODE)                                                  \
200   case WebAssemblyISD::NODE:                                                   \
201     return "WebAssemblyISD::" #NODE;
202 #include "WebAssemblyISD.def"
203 #undef HANDLE_NODETYPE
204   }
205   return nullptr;
206 }
207 
208 //===----------------------------------------------------------------------===//
209 // WebAssembly Lowering private implementation.
210 //===----------------------------------------------------------------------===//
211 
212 //===----------------------------------------------------------------------===//
213 // Lowering Code
214 //===----------------------------------------------------------------------===//
215 
216 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
217   MachineFunction &MF = DAG.getMachineFunction();
218   DAG.getContext()->diagnose(
219       DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
220 }
221 
222 SDValue
223 WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
224                                      SmallVectorImpl<SDValue> &InVals) const {
225   SelectionDAG &DAG = CLI.DAG;
226   SDLoc DL = CLI.DL;
227   SDValue Chain = CLI.Chain;
228   SDValue Callee = CLI.Callee;
229   MachineFunction &MF = DAG.getMachineFunction();
230 
231   CallingConv::ID CallConv = CLI.CallConv;
232   if (CallConv != CallingConv::C &&
233       CallConv != CallingConv::Fast &&
234       CallConv != CallingConv::Cold)
235     fail(DL, DAG,
236          "WebAssembly doesn't support language-specific or target-specific "
237          "calling conventions yet");
238   if (CLI.IsPatchPoint)
239     fail(DL, DAG, "WebAssembly doesn't support patch point yet");
240 
241   // WebAssembly doesn't currently support explicit tail calls. If they are
242   // required, fail. Otherwise, just disable them.
243   if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
244        MF.getTarget().Options.GuaranteedTailCallOpt) ||
245       (CLI.CS && CLI.CS->isMustTailCall()))
246     fail(DL, DAG, "WebAssembly doesn't support tail call yet");
247   CLI.IsTailCall = false;
248 
249   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
250   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
251 
252   bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
253   if (IsStructRet)
254     fail(DL, DAG, "WebAssembly doesn't support struct return yet");
255 
256   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
257   if (Ins.size() > 1)
258     fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
259 
260   bool IsVarArg = CLI.IsVarArg;
261   if (IsVarArg)
262     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
263 
264   // Analyze operands of the call, assigning locations to each operand.
265   SmallVector<CCValAssign, 16> ArgLocs;
266   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
267   unsigned NumBytes = CCInfo.getNextStackOffset();
268 
269   auto PtrVT = getPointerTy(MF.getDataLayout());
270   auto Zero = DAG.getConstant(0, DL, PtrVT, true);
271   auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
272   Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
273 
274   SmallVector<SDValue, 16> Ops;
275   Ops.push_back(Chain);
276   Ops.push_back(Callee);
277   Ops.append(OutVals.begin(), OutVals.end());
278 
279   SmallVector<EVT, 8> Tys;
280   for (const auto &In : Ins)
281     Tys.push_back(In.VT);
282   Tys.push_back(MVT::Other);
283   SDVTList TyList = DAG.getVTList(Tys);
284   SDValue Res =
285       DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
286                   DL, TyList, Ops);
287   if (Ins.empty()) {
288     Chain = Res;
289   } else {
290     InVals.push_back(Res);
291     Chain = Res.getValue(1);
292   }
293 
294   // FIXME: handle CLI.RetSExt and CLI.RetZExt?
295 
296   Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
297 
298   return Chain;
299 }
300 
301 bool WebAssemblyTargetLowering::CanLowerReturn(
302     CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
303     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
304   // WebAssembly can't currently handle returning tuples.
305   return Outs.size() <= 1;
306 }
307 
308 SDValue WebAssemblyTargetLowering::LowerReturn(
309     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
310     const SmallVectorImpl<ISD::OutputArg> &Outs,
311     const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
312     SelectionDAG &DAG) const {
313 
314   assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
315   if (CallConv != CallingConv::C)
316     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
317   if (IsVarArg)
318     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
319 
320   SmallVector<SDValue, 4> RetOps(1, Chain);
321   RetOps.append(OutVals.begin(), OutVals.end());
322   Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
323 
324   return Chain;
325 }
326 
327 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
328     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
329     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
330     SmallVectorImpl<SDValue> &InVals) const {
331   MachineFunction &MF = DAG.getMachineFunction();
332 
333   if (CallConv != CallingConv::C)
334     fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
335   if (IsVarArg)
336     fail(DL, DAG, "WebAssembly doesn't support varargs yet");
337   if (MF.getFunction()->hasStructRetAttr())
338     fail(DL, DAG, "WebAssembly doesn't support struct return yet");
339 
340   unsigned ArgNo = 0;
341   for (const ISD::InputArg &In : Ins) {
342     if (In.Flags.isZExt())
343       fail(DL, DAG, "WebAssembly hasn't implemented zext arguments");
344     if (In.Flags.isSExt())
345       fail(DL, DAG, "WebAssembly hasn't implemented sext arguments");
346     if (In.Flags.isInReg())
347       fail(DL, DAG, "WebAssembly hasn't implemented inreg arguments");
348     if (In.Flags.isSRet())
349       fail(DL, DAG, "WebAssembly hasn't implemented sret arguments");
350     if (In.Flags.isByVal())
351       fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
352     if (In.Flags.isInAlloca())
353       fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
354     if (In.Flags.isNest())
355       fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
356     if (In.Flags.isReturned())
357       fail(DL, DAG, "WebAssembly hasn't implemented returned arguments");
358     if (In.Flags.isInConsecutiveRegs())
359       fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
360     if (In.Flags.isInConsecutiveRegsLast())
361       fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
362     if (In.Flags.isSplit())
363       fail(DL, DAG, "WebAssembly hasn't implemented split arguments");
364     // FIXME Do something with In.getOrigAlign()?
365     InVals.push_back(
366         In.Used
367             ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
368                           DAG.getTargetConstant(ArgNo, DL, MVT::i32))
369             : DAG.getNode(ISD::UNDEF, DL, In.VT));
370     ++ArgNo;
371   }
372 
373   // Record the number of arguments, since argument indices and local variable
374   // indices are in the same index space.
375   MF.getInfo<WebAssemblyFunctionInfo>()->setNumArguments(ArgNo);
376 
377   return Chain;
378 }
379 
380 //===----------------------------------------------------------------------===//
381 //  Custom lowering hooks.
382 //===----------------------------------------------------------------------===//
383 
384 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
385                                                   SelectionDAG &DAG) const {
386   switch (Op.getOpcode()) {
387   default:
388     llvm_unreachable("unimplemented operation lowering");
389     return SDValue();
390   case ISD::GlobalAddress:
391     return LowerGlobalAddress(Op, DAG);
392   case ISD::JumpTable:
393     return LowerJumpTable(Op, DAG);
394   case ISD::BR_JT:
395     return LowerBR_JT(Op, DAG);
396   }
397 }
398 
399 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
400                                                       SelectionDAG &DAG) const {
401   SDLoc DL(Op);
402   const auto *GA = cast<GlobalAddressSDNode>(Op);
403   EVT VT = Op.getValueType();
404   assert(GA->getOffset() == 0 &&
405          "offsets on global addresses are forbidden by isOffsetFoldingLegal");
406   assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
407   if (GA->getAddressSpace() != 0)
408     fail(DL, DAG, "WebAssembly only expects the 0 address space");
409   return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
410                      DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
411 }
412 
413 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
414                                                   SelectionDAG &DAG) const {
415   // There's no need for a Wrapper node because we always incorporate a jump
416   // table operand into a SWITCH instruction, rather than ever materializing
417   // it in a register.
418   const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
419   return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
420                                 JT->getTargetFlags());
421 }
422 
423 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
424                                               SelectionDAG &DAG) const {
425   SDLoc DL(Op);
426   SDValue Chain = Op.getOperand(0);
427   const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
428   SDValue Index = Op.getOperand(2);
429   assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
430 
431   SmallVector<SDValue, 8> Ops;
432   Ops.push_back(Chain);
433   Ops.push_back(Index);
434 
435   MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
436   const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
437 
438   // TODO: For now, we just pick something arbitrary for a default case for now.
439   // We really want to sniff out the guard and put in the real default case (and
440   // delete the guard).
441   Ops.push_back(DAG.getBasicBlock(MBBs[0]));
442 
443   // Add an operand for each case.
444   for (auto MBB : MBBs)
445     Ops.push_back(DAG.getBasicBlock(MBB));
446 
447   return DAG.getNode(WebAssemblyISD::SWITCH, DL, MVT::Other, Ops);
448 }
449 
450 //===----------------------------------------------------------------------===//
451 //                          WebAssembly Optimization Hooks
452 //===----------------------------------------------------------------------===//
453 
454 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
455     const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
456     const TargetMachine &TM) const {
457   // TODO: Be more sophisticated than this.
458   return isa<Function>(GV) ? getTextSection() : getDataSection();
459 }
460