1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 static cl::
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                         cl::desc("Disable CTR loops for PPC"));
28 
29 extern "C" void LLVMInitializePowerPCTarget() {
30   // Register the targets
31   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33 }
34 
35 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
36                                    StringRef CPU, StringRef FS,
37                                    const TargetOptions &Options,
38                                    Reloc::Model RM, CodeModel::Model CM,
39                                    CodeGenOpt::Level OL,
40                                    bool is64Bit)
41   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42     Subtarget(TT, CPU, FS, is64Bit),
43     DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
44     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
45     TLInfo(*this), TSInfo(*this),
46     InstrItins(Subtarget.getInstrItineraryData()) {
47 
48   // The binutils for the BG/P are too old for CFI.
49   if (Subtarget.isBGP())
50     setMCUseCFI(false);
51   initAsmInfo();
52 }
53 
54 void PPC32TargetMachine::anchor() { }
55 
56 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
57                                        StringRef CPU, StringRef FS,
58                                        const TargetOptions &Options,
59                                        Reloc::Model RM, CodeModel::Model CM,
60                                        CodeGenOpt::Level OL)
61   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
62 }
63 
64 void PPC64TargetMachine::anchor() { }
65 
66 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
67                                        StringRef CPU,  StringRef FS,
68                                        const TargetOptions &Options,
69                                        Reloc::Model RM, CodeModel::Model CM,
70                                        CodeGenOpt::Level OL)
71   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
72 }
73 
74 
75 //===----------------------------------------------------------------------===//
76 // Pass Pipeline Configuration
77 //===----------------------------------------------------------------------===//
78 
79 namespace {
80 /// PPC Code Generator Pass Configuration Options.
81 class PPCPassConfig : public TargetPassConfig {
82 public:
83   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
84     : TargetPassConfig(TM, PM) {}
85 
86   PPCTargetMachine &getPPCTargetMachine() const {
87     return getTM<PPCTargetMachine>();
88   }
89 
90   const PPCSubtarget &getPPCSubtarget() const {
91     return *getPPCTargetMachine().getSubtargetImpl();
92   }
93 
94   virtual bool addPreISel();
95   virtual bool addILPOpts();
96   virtual bool addInstSelector();
97   virtual bool addPreSched2();
98   virtual bool addPreEmitPass();
99 };
100 } // namespace
101 
102 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
103   return new PPCPassConfig(this, PM);
104 }
105 
106 bool PPCPassConfig::addPreISel() {
107   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
108     addPass(createPPCCTRLoops(getPPCTargetMachine()));
109 
110   return false;
111 }
112 
113 bool PPCPassConfig::addILPOpts() {
114   if (getPPCSubtarget().hasISEL()) {
115     addPass(&EarlyIfConverterID);
116     return true;
117   }
118 
119   return false;
120 }
121 
122 bool PPCPassConfig::addInstSelector() {
123   // Install an instruction selector.
124   addPass(createPPCISelDag(getPPCTargetMachine()));
125 
126 #ifndef NDEBUG
127   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
128     addPass(createPPCCTRLoopsVerify());
129 #endif
130 
131   return false;
132 }
133 
134 bool PPCPassConfig::addPreSched2() {
135   if (getOptLevel() != CodeGenOpt::None)
136     addPass(&IfConverterID);
137 
138   return true;
139 }
140 
141 bool PPCPassConfig::addPreEmitPass() {
142   if (getOptLevel() != CodeGenOpt::None)
143     addPass(createPPCEarlyReturnPass());
144   // Must run branch selection immediately preceding the asm printer.
145   addPass(createPPCBranchSelectionPass());
146   return false;
147 }
148 
149 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
150                                       JITCodeEmitter &JCE) {
151   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
152   // writing?
153   Subtarget.SetJITMode();
154 
155   // Machine code emitter pass for PowerPC.
156   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
157 
158   return false;
159 }
160 
161 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
162   // Add first the target-independent BasicTTI pass, then our PPC pass. This
163   // allows the PPC pass to delegate to the target independent layer when
164   // appropriate.
165   PM.add(createBasicTargetTransformInfoPass(this));
166   PM.add(createPPCTargetTransformInfoPass(this));
167 }
168 
169