1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "PPC.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/CodeGen/MachineScheduler.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CodeGen.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include <cassert>
39 #include <memory>
40 #include <string>
41 
42 using namespace llvm;
43 
44 
45 static cl::opt<bool>
46     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
47                            cl::desc("enable coalescing of duplicate branches for PPC"));
48 static cl::
49 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
50                         cl::desc("Disable CTR loops for PPC"));
51 
52 static cl::
53 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
54                             cl::desc("Disable PPC loop preinc prep"));
55 
56 static cl::opt<bool>
57 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
58   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
59 
60 static cl::
61 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
62                                 cl::desc("Disable VSX Swap Removal for PPC"));
63 
64 static cl::
65 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
66                               cl::desc("Disable QPX load splat simplification"));
67 
68 static cl::
69 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
70                             cl::desc("Disable machine peepholes for PPC"));
71 
72 static cl::opt<bool>
73 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
74              cl::desc("Enable optimizations on complex GEPs"),
75              cl::init(true));
76 
77 static cl::opt<bool>
78 EnablePrefetch("enable-ppc-prefetching",
79                   cl::desc("disable software prefetching on PPC"),
80                   cl::init(false), cl::Hidden);
81 
82 static cl::opt<bool>
83 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
84                       cl::desc("Add extra TOC register dependencies"),
85                       cl::init(true), cl::Hidden);
86 
87 static cl::opt<bool>
88 EnableMachineCombinerPass("ppc-machine-combiner",
89                           cl::desc("Enable the machine combiner pass"),
90                           cl::init(true), cl::Hidden);
91 
92 static cl::opt<bool>
93   ReduceCRLogical("ppc-reduce-cr-logicals",
94                   cl::desc("Expand eligible cr-logical binary ops to branches"),
95                   cl::init(false), cl::Hidden);
96 extern "C" void LLVMInitializePowerPCTarget() {
97   // Register the targets
98   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
99   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
100   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
101 
102   PassRegistry &PR = *PassRegistry::getPassRegistry();
103   initializePPCBoolRetToIntPass(PR);
104   initializePPCExpandISELPass(PR);
105   initializePPCPreEmitPeepholePass(PR);
106   initializePPCTLSDynamicCallPass(PR);
107   initializePPCMIPeepholePass(PR);
108 }
109 
110 /// Return the datalayout string of a subtarget.
111 static std::string getDataLayoutString(const Triple &T) {
112   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
113   std::string Ret;
114 
115   // Most PPC* platforms are big endian, PPC64LE is little endian.
116   if (T.getArch() == Triple::ppc64le)
117     Ret = "e";
118   else
119     Ret = "E";
120 
121   Ret += DataLayout::getManglingComponent(T);
122 
123   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
124   // pointers.
125   if (!is64Bit || T.getOS() == Triple::Lv2)
126     Ret += "-p:32:32";
127 
128   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
129   // documentation are wrong; these are correct (i.e. "what gcc does").
130   if (is64Bit || !T.isOSDarwin())
131     Ret += "-i64:64";
132   else
133     Ret += "-f64:32:64";
134 
135   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
136   if (is64Bit)
137     Ret += "-n32:64";
138   else
139     Ret += "-n32";
140 
141   return Ret;
142 }
143 
144 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
145                                       const Triple &TT) {
146   std::string FullFS = FS;
147 
148   // Make sure 64-bit features are available when CPUname is generic
149   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
150     if (!FullFS.empty())
151       FullFS = "+64bit," + FullFS;
152     else
153       FullFS = "+64bit";
154   }
155 
156   if (OL >= CodeGenOpt::Default) {
157     if (!FullFS.empty())
158       FullFS = "+crbits," + FullFS;
159     else
160       FullFS = "+crbits";
161   }
162 
163   if (OL != CodeGenOpt::None) {
164     if (!FullFS.empty())
165       FullFS = "+invariant-function-descriptors," + FullFS;
166     else
167       FullFS = "+invariant-function-descriptors";
168   }
169 
170   return FullFS;
171 }
172 
173 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
174   // If it isn't a Mach-O file then it's going to be a linux ELF
175   // object file.
176   if (TT.isOSDarwin())
177     return llvm::make_unique<TargetLoweringObjectFileMachO>();
178 
179   return llvm::make_unique<PPC64LinuxTargetObjectFile>();
180 }
181 
182 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
183                                                  const TargetOptions &Options) {
184   if (TT.isOSDarwin())
185     report_fatal_error("Darwin is no longer supported for PowerPC");
186 
187   if (Options.MCOptions.getABIName().startswith("elfv1"))
188     return PPCTargetMachine::PPC_ABI_ELFv1;
189   else if (Options.MCOptions.getABIName().startswith("elfv2"))
190     return PPCTargetMachine::PPC_ABI_ELFv2;
191 
192   assert(Options.MCOptions.getABIName().empty() &&
193          "Unknown target-abi option!");
194 
195   if (TT.isMacOSX())
196     return PPCTargetMachine::PPC_ABI_UNKNOWN;
197 
198   switch (TT.getArch()) {
199   case Triple::ppc64le:
200     return PPCTargetMachine::PPC_ABI_ELFv2;
201   case Triple::ppc64:
202     return PPCTargetMachine::PPC_ABI_ELFv1;
203   default:
204     return PPCTargetMachine::PPC_ABI_UNKNOWN;
205   }
206 }
207 
208 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
209                                            Optional<Reloc::Model> RM) {
210   if (RM.hasValue())
211     return *RM;
212 
213   // Darwin defaults to dynamic-no-pic.
214   if (TT.isOSDarwin())
215     return Reloc::DynamicNoPIC;
216 
217   // Non-darwin 64-bit platforms are PIC by default.
218   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)
219     return Reloc::PIC_;
220 
221   // 32-bit is static by default.
222   return Reloc::Static;
223 }
224 
225 static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
226                                               Optional<CodeModel::Model> CM,
227                                               bool JIT) {
228   if (CM)
229     return *CM;
230   if (!TT.isOSDarwin() && !JIT &&
231       (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
232     return CodeModel::Medium;
233   return CodeModel::Small;
234 }
235 
236 // The FeatureString here is a little subtle. We are modifying the feature
237 // string with what are (currently) non-function specific overrides as it goes
238 // into the LLVMTargetMachine constructor and then using the stored value in the
239 // Subtarget constructor below it.
240 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
241                                    StringRef CPU, StringRef FS,
242                                    const TargetOptions &Options,
243                                    Optional<Reloc::Model> RM,
244                                    Optional<CodeModel::Model> CM,
245                                    CodeGenOpt::Level OL, bool JIT)
246     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
247                         computeFSAdditions(FS, OL, TT), Options,
248                         getEffectiveRelocModel(TT, RM),
249                         getEffectiveCodeModel(TT, CM, JIT), OL),
250       TLOF(createTLOF(getTargetTriple())),
251       TargetABI(computeTargetABI(TT, Options)) {
252   initAsmInfo();
253 }
254 
255 PPCTargetMachine::~PPCTargetMachine() = default;
256 
257 const PPCSubtarget *
258 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
259   Attribute CPUAttr = F.getFnAttribute("target-cpu");
260   Attribute FSAttr = F.getFnAttribute("target-features");
261 
262   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
263                         ? CPUAttr.getValueAsString().str()
264                         : TargetCPU;
265   std::string FS = !FSAttr.hasAttribute(Attribute::None)
266                        ? FSAttr.getValueAsString().str()
267                        : TargetFS;
268 
269   // FIXME: This is related to the code below to reset the target options,
270   // we need to know whether or not the soft float flag is set on the
271   // function before we can generate a subtarget. We also need to use
272   // it as a key for the subtarget since that can be the only difference
273   // between two functions.
274   bool SoftFloat =
275       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
276   // If the soft float attribute is set on the function turn on the soft float
277   // subtarget feature.
278   if (SoftFloat)
279     FS += FS.empty() ? "-hard-float" : ",-hard-float";
280 
281   auto &I = SubtargetMap[CPU + FS];
282   if (!I) {
283     // This needs to be done before we create a new subtarget since any
284     // creation will depend on the TM and the code generation flags on the
285     // function that reside in TargetOptions.
286     resetTargetOptions(F);
287     I = llvm::make_unique<PPCSubtarget>(
288         TargetTriple, CPU,
289         // FIXME: It would be good to have the subtarget additions here
290         // not necessary. Anything that turns them on/off (overrides) ends
291         // up being put at the end of the feature string, but the defaults
292         // shouldn't require adding them. Fixing this means pulling Feature64Bit
293         // out of most of the target cpus in the .td file and making it set only
294         // as part of initialization via the TargetTriple.
295         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
296   }
297   return I.get();
298 }
299 
300 //===----------------------------------------------------------------------===//
301 // Pass Pipeline Configuration
302 //===----------------------------------------------------------------------===//
303 
304 namespace {
305 
306 /// PPC Code Generator Pass Configuration Options.
307 class PPCPassConfig : public TargetPassConfig {
308 public:
309   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
310     : TargetPassConfig(TM, PM) {
311     // At any optimization level above -O0 we use the Machine Scheduler and not
312     // the default Post RA List Scheduler.
313     if (TM.getOptLevel() != CodeGenOpt::None)
314       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
315   }
316 
317   PPCTargetMachine &getPPCTargetMachine() const {
318     return getTM<PPCTargetMachine>();
319   }
320 
321   void addIRPasses() override;
322   bool addPreISel() override;
323   bool addILPOpts() override;
324   bool addInstSelector() override;
325   void addMachineSSAOptimization() override;
326   void addPreRegAlloc() override;
327   void addPreSched2() override;
328   void addPreEmitPass() override;
329 };
330 
331 } // end anonymous namespace
332 
333 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
334   return new PPCPassConfig(*this, PM);
335 }
336 
337 void PPCPassConfig::addIRPasses() {
338   if (TM->getOptLevel() != CodeGenOpt::None)
339     addPass(createPPCBoolRetToIntPass());
340   addPass(createAtomicExpandPass());
341 
342   // For the BG/Q (or if explicitly requested), add explicit data prefetch
343   // intrinsics.
344   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
345                         getOptLevel() != CodeGenOpt::None;
346   if (EnablePrefetch.getNumOccurrences() > 0)
347     UsePrefetching = EnablePrefetch;
348   if (UsePrefetching)
349     addPass(createLoopDataPrefetchPass());
350 
351   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
352     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
353     // and lower a GEP with multiple indices to either arithmetic operations or
354     // multiple GEPs with single index.
355     addPass(createSeparateConstOffsetFromGEPPass(true));
356     // Call EarlyCSE pass to find and remove subexpressions in the lowered
357     // result.
358     addPass(createEarlyCSEPass());
359     // Do loop invariant code motion in case part of the lowered result is
360     // invariant.
361     addPass(createLICMPass());
362   }
363 
364   TargetPassConfig::addIRPasses();
365 }
366 
367 bool PPCPassConfig::addPreISel() {
368   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
369     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
370 
371   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
372     addPass(createPPCCTRLoops());
373 
374   return false;
375 }
376 
377 bool PPCPassConfig::addILPOpts() {
378   addPass(&EarlyIfConverterID);
379 
380   if (EnableMachineCombinerPass)
381     addPass(&MachineCombinerID);
382 
383   return true;
384 }
385 
386 bool PPCPassConfig::addInstSelector() {
387   // Install an instruction selector.
388   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
389 
390 #ifndef NDEBUG
391   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
392     addPass(createPPCCTRLoopsVerify());
393 #endif
394 
395   addPass(createPPCVSXCopyPass());
396   return false;
397 }
398 
399 void PPCPassConfig::addMachineSSAOptimization() {
400   // PPCBranchCoalescingPass need to be done before machine sinking
401   // since it merges empty blocks.
402   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
403     addPass(createPPCBranchCoalescingPass());
404   TargetPassConfig::addMachineSSAOptimization();
405   // For little endian, remove where possible the vector swap instructions
406   // introduced at code generation to normalize vector element order.
407   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
408       !DisableVSXSwapRemoval)
409     addPass(createPPCVSXSwapRemovalPass());
410   // Reduce the number of cr-logical ops.
411   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
412     addPass(createPPCReduceCRLogicalsPass());
413   // Target-specific peephole cleanups performed after instruction
414   // selection.
415   if (!DisableMIPeephole) {
416     addPass(createPPCMIPeepholePass());
417     addPass(&DeadMachineInstructionElimID);
418   }
419 }
420 
421 void PPCPassConfig::addPreRegAlloc() {
422   if (getOptLevel() != CodeGenOpt::None) {
423     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
424     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
425                &PPCVSXFMAMutateID);
426   }
427 
428   // FIXME: We probably don't need to run these for -fPIE.
429   if (getPPCTargetMachine().isPositionIndependent()) {
430     // FIXME: LiveVariables should not be necessary here!
431     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
432     // LiveVariables. This (unnecessary) dependency has been removed now,
433     // however a stage-2 clang build fails without LiveVariables computed here.
434     addPass(&LiveVariablesID, false);
435     addPass(createPPCTLSDynamicCallPass());
436   }
437   if (EnableExtraTOCRegDeps)
438     addPass(createPPCTOCRegDepsPass());
439 }
440 
441 void PPCPassConfig::addPreSched2() {
442   if (getOptLevel() != CodeGenOpt::None) {
443     addPass(&IfConverterID);
444 
445     // This optimization must happen after anything that might do store-to-load
446     // forwarding. Here we're after RA (and, thus, when spills are inserted)
447     // but before post-RA scheduling.
448     if (!DisableQPXLoadSplat)
449       addPass(createPPCQPXLoadSplatPass());
450   }
451 }
452 
453 void PPCPassConfig::addPreEmitPass() {
454   addPass(createPPCPreEmitPeepholePass());
455   addPass(createPPCExpandISELPass());
456 
457   if (getOptLevel() != CodeGenOpt::None)
458     addPass(createPPCEarlyReturnPass(), false);
459   // Must run branch selection immediately preceding the asm printer.
460   addPass(createPPCBranchSelectionPass(), false);
461 }
462 
463 TargetTransformInfo
464 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
465   return TargetTransformInfo(PPCTTIImpl(this, F));
466 }
467