1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPC.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Target/TargetOptions.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 using namespace llvm;
22 
23 extern "C" void LLVMInitializePowerPCTarget() {
24   // Register the targets
25   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
26   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
27 }
28 
29 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
30                                    StringRef CPU, StringRef FS,
31                                    const TargetOptions &Options,
32                                    Reloc::Model RM, CodeModel::Model CM,
33                                    CodeGenOpt::Level OL,
34                                    bool is64Bit)
35   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
36     Subtarget(TT, CPU, FS, is64Bit),
37     DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
38     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
39     TLInfo(*this), TSInfo(*this),
40     InstrItins(Subtarget.getInstrItineraryData()) {
41 }
42 
43 /// Override this for PowerPC.  Tail merging happily breaks up instruction issue
44 /// groups, which typically degrades performance.
45 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
46 
47 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
48                                        StringRef CPU, StringRef FS,
49                                        const TargetOptions &Options,
50                                        Reloc::Model RM, CodeModel::Model CM,
51                                        CodeGenOpt::Level OL)
52   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
53 }
54 
55 
56 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
57                                        StringRef CPU,  StringRef FS,
58                                        const TargetOptions &Options,
59                                        Reloc::Model RM, CodeModel::Model CM,
60                                        CodeGenOpt::Level OL)
61   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
62 }
63 
64 
65 //===----------------------------------------------------------------------===//
66 // Pass Pipeline Configuration
67 //===----------------------------------------------------------------------===//
68 
69 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) {
70   // Install an instruction selector.
71   PM.add(createPPCISelDag(*this));
72   return false;
73 }
74 
75 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) {
76   // Must run branch selection immediately preceding the asm printer.
77   PM.add(createPPCBranchSelectionPass());
78   return false;
79 }
80 
81 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
82                                       JITCodeEmitter &JCE) {
83   // FIXME: This should be moved to TargetJITInfo!!
84   if (Subtarget.isPPC64())
85     // Temporary workaround for the inability of PPC64 JIT to handle jump
86     // tables.
87     Options.DisableJumpTables = true;
88 
89   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
90   // writing?
91   Subtarget.SetJITMode();
92 
93   // Machine code emitter pass for PowerPC.
94   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
95 
96   return false;
97 }
98