1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "TargetInfo/PowerPCTargetInfo.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Pass.h"
33 #include "llvm/Support/CodeGen.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Transforms/Scalar.h"
39 #include <cassert>
40 #include <memory>
41 #include <string>
42 
43 using namespace llvm;
44 
45 
46 static cl::opt<bool>
47     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
48                            cl::desc("enable coalescing of duplicate branches for PPC"));
49 static cl::
50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
51                         cl::desc("Disable CTR loops for PPC"));
52 
53 static cl::
54 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
55                             cl::desc("Disable PPC loop preinc prep"));
56 
57 static cl::opt<bool>
58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
59   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
60 
61 static cl::
62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
63                                 cl::desc("Disable VSX Swap Removal for PPC"));
64 
65 static cl::
66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
67                               cl::desc("Disable QPX load splat simplification"));
68 
69 static cl::
70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
71                             cl::desc("Disable machine peepholes for PPC"));
72 
73 static cl::opt<bool>
74 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
75              cl::desc("Enable optimizations on complex GEPs"),
76              cl::init(true));
77 
78 static cl::opt<bool>
79 EnablePrefetch("enable-ppc-prefetching",
80                   cl::desc("disable software prefetching on PPC"),
81                   cl::init(false), cl::Hidden);
82 
83 static cl::opt<bool>
84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
85                       cl::desc("Add extra TOC register dependencies"),
86                       cl::init(true), cl::Hidden);
87 
88 static cl::opt<bool>
89 EnableMachineCombinerPass("ppc-machine-combiner",
90                           cl::desc("Enable the machine combiner pass"),
91                           cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool>
94   ReduceCRLogical("ppc-reduce-cr-logicals",
95                   cl::desc("Expand eligible cr-logical binary ops to branches"),
96                   cl::init(false), cl::Hidden);
97 extern "C" void LLVMInitializePowerPCTarget() {
98   // Register the targets
99   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
100   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
101   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
102 
103   PassRegistry &PR = *PassRegistry::getPassRegistry();
104   initializePPCCTRLoopsPass(PR);
105 #ifndef NDEBUG
106   initializePPCCTRLoopsVerifyPass(PR);
107 #endif
108   initializePPCLoopPreIncPrepPass(PR);
109   initializePPCTOCRegDepsPass(PR);
110   initializePPCEarlyReturnPass(PR);
111   initializePPCVSXCopyPass(PR);
112   initializePPCVSXFMAMutatePass(PR);
113   initializePPCVSXSwapRemovalPass(PR);
114   initializePPCReduceCRLogicalsPass(PR);
115   initializePPCBSelPass(PR);
116   initializePPCBranchCoalescingPass(PR);
117   initializePPCQPXLoadSplatPass(PR);
118   initializePPCBoolRetToIntPass(PR);
119   initializePPCExpandISELPass(PR);
120   initializePPCPreEmitPeepholePass(PR);
121   initializePPCTLSDynamicCallPass(PR);
122   initializePPCMIPeepholePass(PR);
123 }
124 
125 /// Return the datalayout string of a subtarget.
126 static std::string getDataLayoutString(const Triple &T) {
127   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
128   std::string Ret;
129 
130   // Most PPC* platforms are big endian, PPC64LE is little endian.
131   if (T.getArch() == Triple::ppc64le)
132     Ret = "e";
133   else
134     Ret = "E";
135 
136   Ret += DataLayout::getManglingComponent(T);
137 
138   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
139   // pointers.
140   if (!is64Bit || T.getOS() == Triple::Lv2)
141     Ret += "-p:32:32";
142 
143   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
144   // documentation are wrong; these are correct (i.e. "what gcc does").
145   if (is64Bit || !T.isOSDarwin())
146     Ret += "-i64:64";
147   else
148     Ret += "-f64:32:64";
149 
150   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
151   if (is64Bit)
152     Ret += "-n32:64";
153   else
154     Ret += "-n32";
155 
156   return Ret;
157 }
158 
159 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
160                                       const Triple &TT) {
161   std::string FullFS = FS;
162 
163   // Make sure 64-bit features are available when CPUname is generic
164   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
165     if (!FullFS.empty())
166       FullFS = "+64bit," + FullFS;
167     else
168       FullFS = "+64bit";
169   }
170 
171   if (OL >= CodeGenOpt::Default) {
172     if (!FullFS.empty())
173       FullFS = "+crbits," + FullFS;
174     else
175       FullFS = "+crbits";
176   }
177 
178   if (OL != CodeGenOpt::None) {
179     if (!FullFS.empty())
180       FullFS = "+invariant-function-descriptors," + FullFS;
181     else
182       FullFS = "+invariant-function-descriptors";
183   }
184 
185   return FullFS;
186 }
187 
188 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
189   // If it isn't a Mach-O file then it's going to be a linux ELF
190   // object file.
191   if (TT.isOSDarwin())
192     return llvm::make_unique<TargetLoweringObjectFileMachO>();
193 
194   return llvm::make_unique<PPC64LinuxTargetObjectFile>();
195 }
196 
197 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
198                                                  const TargetOptions &Options) {
199   if (TT.isOSDarwin())
200     report_fatal_error("Darwin is no longer supported for PowerPC");
201 
202   if (Options.MCOptions.getABIName().startswith("elfv1"))
203     return PPCTargetMachine::PPC_ABI_ELFv1;
204   else if (Options.MCOptions.getABIName().startswith("elfv2"))
205     return PPCTargetMachine::PPC_ABI_ELFv2;
206 
207   assert(Options.MCOptions.getABIName().empty() &&
208          "Unknown target-abi option!");
209 
210   if (TT.isMacOSX())
211     return PPCTargetMachine::PPC_ABI_UNKNOWN;
212 
213   switch (TT.getArch()) {
214   case Triple::ppc64le:
215     return PPCTargetMachine::PPC_ABI_ELFv2;
216   case Triple::ppc64:
217     if (TT.getEnvironment() == llvm::Triple::ELFv2)
218       return PPCTargetMachine::PPC_ABI_ELFv2;
219     return PPCTargetMachine::PPC_ABI_ELFv1;
220   default:
221     return PPCTargetMachine::PPC_ABI_UNKNOWN;
222   }
223 }
224 
225 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
226                                            Optional<Reloc::Model> RM) {
227   if (RM.hasValue())
228     return *RM;
229 
230   // Darwin defaults to dynamic-no-pic.
231   if (TT.isOSDarwin())
232     return Reloc::DynamicNoPIC;
233 
234   // Big Endian PPC is PIC by default.
235   if (TT.getArch() == Triple::ppc64)
236     return Reloc::PIC_;
237 
238   // Rest are static by default.
239   return Reloc::Static;
240 }
241 
242 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
243                                                  Optional<CodeModel::Model> CM,
244                                                  bool JIT) {
245   if (CM) {
246     if (*CM == CodeModel::Tiny)
247       report_fatal_error("Target does not support the tiny CodeModel", false);
248     if (*CM == CodeModel::Kernel)
249       report_fatal_error("Target does not support the kernel CodeModel", false);
250     return *CM;
251   }
252   if (!TT.isOSDarwin() && !JIT &&
253       (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
254     return CodeModel::Medium;
255   return CodeModel::Small;
256 }
257 
258 
259 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
260   ScheduleDAGMILive *DAG =
261     new ScheduleDAGMILive(C, llvm::make_unique<PPCPreRASchedStrategy>(C));
262   // add DAG Mutations here.
263   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
264   return DAG;
265 }
266 
267 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
268   MachineSchedContext *C) {
269   ScheduleDAGMI *DAG =
270     new ScheduleDAGMI(C, llvm::make_unique<PPCPostRASchedStrategy>(C), true);
271   // add DAG Mutations here.
272   return DAG;
273 }
274 
275 // The FeatureString here is a little subtle. We are modifying the feature
276 // string with what are (currently) non-function specific overrides as it goes
277 // into the LLVMTargetMachine constructor and then using the stored value in the
278 // Subtarget constructor below it.
279 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
280                                    StringRef CPU, StringRef FS,
281                                    const TargetOptions &Options,
282                                    Optional<Reloc::Model> RM,
283                                    Optional<CodeModel::Model> CM,
284                                    CodeGenOpt::Level OL, bool JIT)
285     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
286                         computeFSAdditions(FS, OL, TT), Options,
287                         getEffectiveRelocModel(TT, RM),
288                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
289       TLOF(createTLOF(getTargetTriple())),
290       TargetABI(computeTargetABI(TT, Options)) {
291   initAsmInfo();
292 }
293 
294 PPCTargetMachine::~PPCTargetMachine() = default;
295 
296 const PPCSubtarget *
297 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
298   Attribute CPUAttr = F.getFnAttribute("target-cpu");
299   Attribute FSAttr = F.getFnAttribute("target-features");
300 
301   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
302                         ? CPUAttr.getValueAsString().str()
303                         : TargetCPU;
304   std::string FS = !FSAttr.hasAttribute(Attribute::None)
305                        ? FSAttr.getValueAsString().str()
306                        : TargetFS;
307 
308   // FIXME: This is related to the code below to reset the target options,
309   // we need to know whether or not the soft float flag is set on the
310   // function before we can generate a subtarget. We also need to use
311   // it as a key for the subtarget since that can be the only difference
312   // between two functions.
313   bool SoftFloat =
314       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
315   // If the soft float attribute is set on the function turn on the soft float
316   // subtarget feature.
317   if (SoftFloat)
318     FS += FS.empty() ? "-hard-float" : ",-hard-float";
319 
320   auto &I = SubtargetMap[CPU + FS];
321   if (!I) {
322     // This needs to be done before we create a new subtarget since any
323     // creation will depend on the TM and the code generation flags on the
324     // function that reside in TargetOptions.
325     resetTargetOptions(F);
326     I = llvm::make_unique<PPCSubtarget>(
327         TargetTriple, CPU,
328         // FIXME: It would be good to have the subtarget additions here
329         // not necessary. Anything that turns them on/off (overrides) ends
330         // up being put at the end of the feature string, but the defaults
331         // shouldn't require adding them. Fixing this means pulling Feature64Bit
332         // out of most of the target cpus in the .td file and making it set only
333         // as part of initialization via the TargetTriple.
334         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
335   }
336   return I.get();
337 }
338 
339 //===----------------------------------------------------------------------===//
340 // Pass Pipeline Configuration
341 //===----------------------------------------------------------------------===//
342 
343 namespace {
344 
345 /// PPC Code Generator Pass Configuration Options.
346 class PPCPassConfig : public TargetPassConfig {
347 public:
348   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
349     : TargetPassConfig(TM, PM) {
350     // At any optimization level above -O0 we use the Machine Scheduler and not
351     // the default Post RA List Scheduler.
352     if (TM.getOptLevel() != CodeGenOpt::None)
353       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
354   }
355 
356   PPCTargetMachine &getPPCTargetMachine() const {
357     return getTM<PPCTargetMachine>();
358   }
359 
360   void addIRPasses() override;
361   bool addPreISel() override;
362   bool addILPOpts() override;
363   bool addInstSelector() override;
364   void addMachineSSAOptimization() override;
365   void addPreRegAlloc() override;
366   void addPreSched2() override;
367   void addPreEmitPass() override;
368   ScheduleDAGInstrs *
369   createMachineScheduler(MachineSchedContext *C) const override {
370     const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
371     if (ST.usePPCPreRASchedStrategy())
372       return createPPCMachineScheduler(C);
373     return nullptr;
374   }
375   ScheduleDAGInstrs *
376   createPostMachineScheduler(MachineSchedContext *C) const override {
377     const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
378     if (ST.usePPCPostRASchedStrategy())
379       return createPPCPostMachineScheduler(C);
380     return nullptr;
381   }
382 };
383 
384 } // end anonymous namespace
385 
386 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
387   return new PPCPassConfig(*this, PM);
388 }
389 
390 void PPCPassConfig::addIRPasses() {
391   if (TM->getOptLevel() != CodeGenOpt::None)
392     addPass(createPPCBoolRetToIntPass());
393   addPass(createAtomicExpandPass());
394 
395   // For the BG/Q (or if explicitly requested), add explicit data prefetch
396   // intrinsics.
397   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
398                         getOptLevel() != CodeGenOpt::None;
399   if (EnablePrefetch.getNumOccurrences() > 0)
400     UsePrefetching = EnablePrefetch;
401   if (UsePrefetching)
402     addPass(createLoopDataPrefetchPass());
403 
404   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
405     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
406     // and lower a GEP with multiple indices to either arithmetic operations or
407     // multiple GEPs with single index.
408     addPass(createSeparateConstOffsetFromGEPPass(true));
409     // Call EarlyCSE pass to find and remove subexpressions in the lowered
410     // result.
411     addPass(createEarlyCSEPass());
412     // Do loop invariant code motion in case part of the lowered result is
413     // invariant.
414     addPass(createLICMPass());
415   }
416 
417   TargetPassConfig::addIRPasses();
418 }
419 
420 bool PPCPassConfig::addPreISel() {
421   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
422     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
423 
424   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
425     addPass(createPPCCTRLoops());
426 
427   return false;
428 }
429 
430 bool PPCPassConfig::addILPOpts() {
431   addPass(&EarlyIfConverterID);
432 
433   if (EnableMachineCombinerPass)
434     addPass(&MachineCombinerID);
435 
436   return true;
437 }
438 
439 bool PPCPassConfig::addInstSelector() {
440   // Install an instruction selector.
441   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
442 
443 #ifndef NDEBUG
444   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
445     addPass(createPPCCTRLoopsVerify());
446 #endif
447 
448   addPass(createPPCVSXCopyPass());
449   return false;
450 }
451 
452 void PPCPassConfig::addMachineSSAOptimization() {
453   // PPCBranchCoalescingPass need to be done before machine sinking
454   // since it merges empty blocks.
455   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
456     addPass(createPPCBranchCoalescingPass());
457   TargetPassConfig::addMachineSSAOptimization();
458   // For little endian, remove where possible the vector swap instructions
459   // introduced at code generation to normalize vector element order.
460   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
461       !DisableVSXSwapRemoval)
462     addPass(createPPCVSXSwapRemovalPass());
463   // Reduce the number of cr-logical ops.
464   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
465     addPass(createPPCReduceCRLogicalsPass());
466   // Target-specific peephole cleanups performed after instruction
467   // selection.
468   if (!DisableMIPeephole) {
469     addPass(createPPCMIPeepholePass());
470     addPass(&DeadMachineInstructionElimID);
471   }
472 }
473 
474 void PPCPassConfig::addPreRegAlloc() {
475   if (getOptLevel() != CodeGenOpt::None) {
476     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
477     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
478                &PPCVSXFMAMutateID);
479   }
480 
481   // FIXME: We probably don't need to run these for -fPIE.
482   if (getPPCTargetMachine().isPositionIndependent()) {
483     // FIXME: LiveVariables should not be necessary here!
484     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
485     // LiveVariables. This (unnecessary) dependency has been removed now,
486     // however a stage-2 clang build fails without LiveVariables computed here.
487     addPass(&LiveVariablesID, false);
488     addPass(createPPCTLSDynamicCallPass());
489   }
490   if (EnableExtraTOCRegDeps)
491     addPass(createPPCTOCRegDepsPass());
492 }
493 
494 void PPCPassConfig::addPreSched2() {
495   if (getOptLevel() != CodeGenOpt::None) {
496     addPass(&IfConverterID);
497 
498     // This optimization must happen after anything that might do store-to-load
499     // forwarding. Here we're after RA (and, thus, when spills are inserted)
500     // but before post-RA scheduling.
501     if (!DisableQPXLoadSplat)
502       addPass(createPPCQPXLoadSplatPass());
503   }
504 }
505 
506 void PPCPassConfig::addPreEmitPass() {
507   addPass(createPPCPreEmitPeepholePass());
508   addPass(createPPCExpandISELPass());
509 
510   if (getOptLevel() != CodeGenOpt::None)
511     addPass(createPPCEarlyReturnPass(), false);
512   // Must run branch selection immediately preceding the asm printer.
513   addPass(createPPCBranchSelectionPass(), false);
514 }
515 
516 TargetTransformInfo
517 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
518   return TargetTransformInfo(PPCTTIImpl(this, F));
519 }
520 
521 static MachineSchedRegistry
522 PPCPreRASchedRegistry("ppc-prera",
523                       "Run PowerPC PreRA specific scheduler",
524                       createPPCMachineScheduler);
525 
526 static MachineSchedRegistry
527 PPCPostRASchedRegistry("ppc-postra",
528                        "Run PowerPC PostRA specific scheduler",
529                        createPPCPostMachineScheduler);
530