1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "PPC.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Pass.h"
31 #include "llvm/Support/CodeGen.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include <cassert>
38 #include <memory>
39 #include <string>
40 
41 using namespace llvm;
42 
43 
44 static cl::opt<bool>
45     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
46                            cl::desc("enable coalescing of duplicate branches for PPC"));
47 static cl::
48 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
49                         cl::desc("Disable CTR loops for PPC"));
50 
51 static cl::
52 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
53                             cl::desc("Disable PPC loop preinc prep"));
54 
55 static cl::opt<bool>
56 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
57   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
58 
59 static cl::
60 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
61                                 cl::desc("Disable VSX Swap Removal for PPC"));
62 
63 static cl::
64 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
65                               cl::desc("Disable QPX load splat simplification"));
66 
67 static cl::
68 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
69                             cl::desc("Disable machine peepholes for PPC"));
70 
71 static cl::opt<bool>
72 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
73              cl::desc("Enable optimizations on complex GEPs"),
74              cl::init(true));
75 
76 static cl::opt<bool>
77 EnablePrefetch("enable-ppc-prefetching",
78                   cl::desc("disable software prefetching on PPC"),
79                   cl::init(false), cl::Hidden);
80 
81 static cl::opt<bool>
82 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
83                       cl::desc("Add extra TOC register dependencies"),
84                       cl::init(true), cl::Hidden);
85 
86 static cl::opt<bool>
87 EnableMachineCombinerPass("ppc-machine-combiner",
88                           cl::desc("Enable the machine combiner pass"),
89                           cl::init(true), cl::Hidden);
90 
91 extern "C" void LLVMInitializePowerPCTarget() {
92   // Register the targets
93   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
94   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
95   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
96 
97   PassRegistry &PR = *PassRegistry::getPassRegistry();
98   initializePPCBoolRetToIntPass(PR);
99   initializePPCExpandISELPass(PR);
100   initializePPCTLSDynamicCallPass(PR);
101 }
102 
103 /// Return the datalayout string of a subtarget.
104 static std::string getDataLayoutString(const Triple &T) {
105   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
106   std::string Ret;
107 
108   // Most PPC* platforms are big endian, PPC64LE is little endian.
109   if (T.getArch() == Triple::ppc64le)
110     Ret = "e";
111   else
112     Ret = "E";
113 
114   Ret += DataLayout::getManglingComponent(T);
115 
116   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
117   // pointers.
118   if (!is64Bit || T.getOS() == Triple::Lv2)
119     Ret += "-p:32:32";
120 
121   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
122   // documentation are wrong; these are correct (i.e. "what gcc does").
123   if (is64Bit || !T.isOSDarwin())
124     Ret += "-i64:64";
125   else
126     Ret += "-f64:32:64";
127 
128   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
129   if (is64Bit)
130     Ret += "-n32:64";
131   else
132     Ret += "-n32";
133 
134   return Ret;
135 }
136 
137 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
138                                       const Triple &TT) {
139   std::string FullFS = FS;
140 
141   // Make sure 64-bit features are available when CPUname is generic
142   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
143     if (!FullFS.empty())
144       FullFS = "+64bit," + FullFS;
145     else
146       FullFS = "+64bit";
147   }
148 
149   if (OL >= CodeGenOpt::Default) {
150     if (!FullFS.empty())
151       FullFS = "+crbits," + FullFS;
152     else
153       FullFS = "+crbits";
154   }
155 
156   if (OL != CodeGenOpt::None) {
157     if (!FullFS.empty())
158       FullFS = "+invariant-function-descriptors," + FullFS;
159     else
160       FullFS = "+invariant-function-descriptors";
161   }
162 
163   return FullFS;
164 }
165 
166 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
167   // If it isn't a Mach-O file then it's going to be a linux ELF
168   // object file.
169   if (TT.isOSDarwin())
170     return llvm::make_unique<TargetLoweringObjectFileMachO>();
171 
172   return llvm::make_unique<PPC64LinuxTargetObjectFile>();
173 }
174 
175 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
176                                                  const TargetOptions &Options) {
177   if (Options.MCOptions.getABIName().startswith("elfv1"))
178     return PPCTargetMachine::PPC_ABI_ELFv1;
179   else if (Options.MCOptions.getABIName().startswith("elfv2"))
180     return PPCTargetMachine::PPC_ABI_ELFv2;
181 
182   assert(Options.MCOptions.getABIName().empty() &&
183          "Unknown target-abi option!");
184 
185   if (TT.isMacOSX())
186     return PPCTargetMachine::PPC_ABI_UNKNOWN;
187 
188   switch (TT.getArch()) {
189   case Triple::ppc64le:
190     return PPCTargetMachine::PPC_ABI_ELFv2;
191   case Triple::ppc64:
192     return PPCTargetMachine::PPC_ABI_ELFv1;
193   default:
194     return PPCTargetMachine::PPC_ABI_UNKNOWN;
195   }
196 }
197 
198 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
199                                            Optional<Reloc::Model> RM) {
200   if (RM.hasValue())
201     return *RM;
202 
203   // Darwin defaults to dynamic-no-pic.
204   if (TT.isOSDarwin())
205     return Reloc::DynamicNoPIC;
206 
207   // Non-darwin 64-bit platforms are PIC by default.
208   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)
209     return Reloc::PIC_;
210 
211   // 32-bit is static by default.
212   return Reloc::Static;
213 }
214 
215 static CodeModel::Model getEffectiveCodeModel(const Triple &TT,
216                                               Optional<CodeModel::Model> CM,
217                                               bool JIT) {
218   if (CM)
219     return *CM;
220   if (!TT.isOSDarwin() && !JIT &&
221       (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
222     return CodeModel::Medium;
223   return CodeModel::Small;
224 }
225 
226 // The FeatureString here is a little subtle. We are modifying the feature
227 // string with what are (currently) non-function specific overrides as it goes
228 // into the LLVMTargetMachine constructor and then using the stored value in the
229 // Subtarget constructor below it.
230 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
231                                    StringRef CPU, StringRef FS,
232                                    const TargetOptions &Options,
233                                    Optional<Reloc::Model> RM,
234                                    Optional<CodeModel::Model> CM,
235                                    CodeGenOpt::Level OL, bool JIT)
236     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
237                         computeFSAdditions(FS, OL, TT), Options,
238                         getEffectiveRelocModel(TT, RM),
239                         getEffectiveCodeModel(TT, CM, JIT), OL),
240       TLOF(createTLOF(getTargetTriple())),
241       TargetABI(computeTargetABI(TT, Options)) {
242   initAsmInfo();
243 }
244 
245 PPCTargetMachine::~PPCTargetMachine() = default;
246 
247 const PPCSubtarget *
248 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
249   Attribute CPUAttr = F.getFnAttribute("target-cpu");
250   Attribute FSAttr = F.getFnAttribute("target-features");
251 
252   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
253                         ? CPUAttr.getValueAsString().str()
254                         : TargetCPU;
255   std::string FS = !FSAttr.hasAttribute(Attribute::None)
256                        ? FSAttr.getValueAsString().str()
257                        : TargetFS;
258 
259   // FIXME: This is related to the code below to reset the target options,
260   // we need to know whether or not the soft float flag is set on the
261   // function before we can generate a subtarget. We also need to use
262   // it as a key for the subtarget since that can be the only difference
263   // between two functions.
264   bool SoftFloat =
265       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
266   // If the soft float attribute is set on the function turn on the soft float
267   // subtarget feature.
268   if (SoftFloat)
269     FS += FS.empty() ? "-hard-float" : ",-hard-float";
270 
271   auto &I = SubtargetMap[CPU + FS];
272   if (!I) {
273     // This needs to be done before we create a new subtarget since any
274     // creation will depend on the TM and the code generation flags on the
275     // function that reside in TargetOptions.
276     resetTargetOptions(F);
277     I = llvm::make_unique<PPCSubtarget>(
278         TargetTriple, CPU,
279         // FIXME: It would be good to have the subtarget additions here
280         // not necessary. Anything that turns them on/off (overrides) ends
281         // up being put at the end of the feature string, but the defaults
282         // shouldn't require adding them. Fixing this means pulling Feature64Bit
283         // out of most of the target cpus in the .td file and making it set only
284         // as part of initialization via the TargetTriple.
285         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
286   }
287   return I.get();
288 }
289 
290 //===----------------------------------------------------------------------===//
291 // Pass Pipeline Configuration
292 //===----------------------------------------------------------------------===//
293 
294 namespace {
295 
296 /// PPC Code Generator Pass Configuration Options.
297 class PPCPassConfig : public TargetPassConfig {
298 public:
299   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
300     : TargetPassConfig(TM, PM) {}
301 
302   PPCTargetMachine &getPPCTargetMachine() const {
303     return getTM<PPCTargetMachine>();
304   }
305 
306   void addIRPasses() override;
307   bool addPreISel() override;
308   bool addILPOpts() override;
309   bool addInstSelector() override;
310   void addMachineSSAOptimization() override;
311   void addPreRegAlloc() override;
312   void addPreSched2() override;
313   void addPreEmitPass() override;
314 };
315 
316 } // end anonymous namespace
317 
318 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
319   return new PPCPassConfig(*this, PM);
320 }
321 
322 void PPCPassConfig::addIRPasses() {
323   if (TM->getOptLevel() != CodeGenOpt::None)
324     addPass(createPPCBoolRetToIntPass());
325   addPass(createAtomicExpandPass());
326 
327   // For the BG/Q (or if explicitly requested), add explicit data prefetch
328   // intrinsics.
329   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
330                         getOptLevel() != CodeGenOpt::None;
331   if (EnablePrefetch.getNumOccurrences() > 0)
332     UsePrefetching = EnablePrefetch;
333   if (UsePrefetching)
334     addPass(createLoopDataPrefetchPass());
335 
336   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
337     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
338     // and lower a GEP with multiple indices to either arithmetic operations or
339     // multiple GEPs with single index.
340     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
341     // Call EarlyCSE pass to find and remove subexpressions in the lowered
342     // result.
343     addPass(createEarlyCSEPass());
344     // Do loop invariant code motion in case part of the lowered result is
345     // invariant.
346     addPass(createLICMPass());
347   }
348 
349   TargetPassConfig::addIRPasses();
350 }
351 
352 bool PPCPassConfig::addPreISel() {
353   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
354     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
355 
356   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
357     addPass(createPPCCTRLoops());
358 
359   return false;
360 }
361 
362 bool PPCPassConfig::addILPOpts() {
363   addPass(&EarlyIfConverterID);
364 
365   if (EnableMachineCombinerPass)
366     addPass(&MachineCombinerID);
367 
368   return true;
369 }
370 
371 bool PPCPassConfig::addInstSelector() {
372   // Install an instruction selector.
373   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
374 
375 #ifndef NDEBUG
376   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
377     addPass(createPPCCTRLoopsVerify());
378 #endif
379 
380   addPass(createPPCVSXCopyPass());
381   return false;
382 }
383 
384 void PPCPassConfig::addMachineSSAOptimization() {
385   // PPCBranchCoalescingPass need to be done before machine sinking
386   // since it merges empty blocks.
387   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
388     addPass(createPPCBranchCoalescingPass());
389   TargetPassConfig::addMachineSSAOptimization();
390   // For little endian, remove where possible the vector swap instructions
391   // introduced at code generation to normalize vector element order.
392   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
393       !DisableVSXSwapRemoval)
394     addPass(createPPCVSXSwapRemovalPass());
395   // Target-specific peephole cleanups performed after instruction
396   // selection.
397   if (!DisableMIPeephole) {
398     addPass(createPPCMIPeepholePass());
399     addPass(&DeadMachineInstructionElimID);
400   }
401 }
402 
403 void PPCPassConfig::addPreRegAlloc() {
404   if (getOptLevel() != CodeGenOpt::None) {
405     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
406     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
407                &PPCVSXFMAMutateID);
408   }
409 
410   // FIXME: We probably don't need to run these for -fPIE.
411   if (getPPCTargetMachine().isPositionIndependent()) {
412     // FIXME: LiveVariables should not be necessary here!
413     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
414     // LiveVariables. This (unnecessary) dependency has been removed now,
415     // however a stage-2 clang build fails without LiveVariables computed here.
416     addPass(&LiveVariablesID, false);
417     addPass(createPPCTLSDynamicCallPass());
418   }
419   if (EnableExtraTOCRegDeps)
420     addPass(createPPCTOCRegDepsPass());
421 }
422 
423 void PPCPassConfig::addPreSched2() {
424   if (getOptLevel() != CodeGenOpt::None) {
425     addPass(&IfConverterID);
426 
427     // This optimization must happen after anything that might do store-to-load
428     // forwarding. Here we're after RA (and, thus, when spills are inserted)
429     // but before post-RA scheduling.
430     if (!DisableQPXLoadSplat)
431       addPass(createPPCQPXLoadSplatPass());
432   }
433 }
434 
435 void PPCPassConfig::addPreEmitPass() {
436   addPass(createPPCExpandISELPass());
437 
438   if (getOptLevel() != CodeGenOpt::None)
439     addPass(createPPCEarlyReturnPass(), false);
440   // Must run branch selection immediately preceding the asm printer.
441   addPass(createPPCBranchSelectionPass(), false);
442 }
443 
444 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
445   return TargetIRAnalysis([this](const Function &F) {
446     return TargetTransformInfo(PPCTTIImpl(this, F));
447   });
448 }
449