1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCMacroFusion.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetObjectFile.h"
20 #include "PPCTargetTransformInfo.h"
21 #include "TargetInfo/PowerPCTargetInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Analysis/TargetTransformInfo.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/Localizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/MachineScheduler.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/InitializePasses.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Target/TargetLoweringObjectFile.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <cassert>
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 
54 static cl::opt<bool>
55     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
56                            cl::desc("enable coalescing of duplicate branches for PPC"));
57 static cl::
58 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
59                         cl::desc("Disable CTR loops for PPC"));
60 
61 static cl::
62 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
63                             cl::desc("Disable PPC loop instr form prep"));
64 
65 static cl::opt<bool>
66 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
67   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
68 
69 static cl::
70 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
71                                 cl::desc("Disable VSX Swap Removal for PPC"));
72 
73 static cl::
74 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
75                             cl::desc("Disable machine peepholes for PPC"));
76 
77 static cl::opt<bool>
78 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
79              cl::desc("Enable optimizations on complex GEPs"),
80              cl::init(true));
81 
82 static cl::opt<bool>
83 EnablePrefetch("enable-ppc-prefetching",
84                   cl::desc("enable software prefetching on PPC"),
85                   cl::init(false), cl::Hidden);
86 
87 static cl::opt<bool>
88 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
89                       cl::desc("Add extra TOC register dependencies"),
90                       cl::init(true), cl::Hidden);
91 
92 static cl::opt<bool>
93 EnableMachineCombinerPass("ppc-machine-combiner",
94                           cl::desc("Enable the machine combiner pass"),
95                           cl::init(true), cl::Hidden);
96 
97 static cl::opt<bool>
98   ReduceCRLogical("ppc-reduce-cr-logicals",
99                   cl::desc("Expand eligible cr-logical binary ops to branches"),
100                   cl::init(true), cl::Hidden);
101 
102 static cl::opt<bool> EnablePPCGenScalarMASSEntries(
103     "enable-ppc-gen-scalar-mass", cl::init(false),
104     cl::desc("Enable lowering math functions to their corresponding MASS "
105              "(scalar) entries"),
106     cl::Hidden);
107 
108 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
109   // Register the targets
110   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
111   RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
112   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
113   RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
114 
115   PassRegistry &PR = *PassRegistry::getPassRegistry();
116 #ifndef NDEBUG
117   initializePPCCTRLoopsVerifyPass(PR);
118 #endif
119   initializePPCLoopInstrFormPrepPass(PR);
120   initializePPCTOCRegDepsPass(PR);
121   initializePPCEarlyReturnPass(PR);
122   initializePPCVSXCopyPass(PR);
123   initializePPCVSXFMAMutatePass(PR);
124   initializePPCVSXSwapRemovalPass(PR);
125   initializePPCReduceCRLogicalsPass(PR);
126   initializePPCBSelPass(PR);
127   initializePPCBranchCoalescingPass(PR);
128   initializePPCBoolRetToIntPass(PR);
129   initializePPCExpandISELPass(PR);
130   initializePPCPreEmitPeepholePass(PR);
131   initializePPCTLSDynamicCallPass(PR);
132   initializePPCMIPeepholePass(PR);
133   initializePPCLowerMASSVEntriesPass(PR);
134   initializePPCGenScalarMASSEntriesPass(PR);
135   initializePPCExpandAtomicPseudoPass(PR);
136   initializeGlobalISel(PR);
137 }
138 
139 static bool isLittleEndianTriple(const Triple &T) {
140   return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
141 }
142 
143 /// Return the datalayout string of a subtarget.
144 static std::string getDataLayoutString(const Triple &T) {
145   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
146   std::string Ret;
147 
148   // Most PPC* platforms are big endian, PPC(64)LE is little endian.
149   if (isLittleEndianTriple(T))
150     Ret = "e";
151   else
152     Ret = "E";
153 
154   Ret += DataLayout::getManglingComponent(T);
155 
156   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
157   // pointers.
158   if (!is64Bit || T.getOS() == Triple::Lv2)
159     Ret += "-p:32:32";
160 
161   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
162   // documentation are wrong; these are correct (i.e. "what gcc does").
163   Ret += "-i64:64";
164 
165   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
166   if (is64Bit)
167     Ret += "-n32:64";
168   else
169     Ret += "-n32";
170 
171   // Specify the vector alignment explicitly. For v256i1 and v512i1, the
172   // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
173   // which is 256 and 512 bytes - way over aligned.
174   if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
175     Ret += "-S128-v256:256:256-v512:512:512";
176 
177   return Ret;
178 }
179 
180 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
181                                       const Triple &TT) {
182   std::string FullFS = std::string(FS);
183 
184   // Make sure 64-bit features are available when CPUname is generic
185   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
186     if (!FullFS.empty())
187       FullFS = "+64bit," + FullFS;
188     else
189       FullFS = "+64bit";
190   }
191 
192   if (OL >= CodeGenOpt::Default) {
193     if (!FullFS.empty())
194       FullFS = "+crbits," + FullFS;
195     else
196       FullFS = "+crbits";
197   }
198 
199   if (OL != CodeGenOpt::None) {
200     if (!FullFS.empty())
201       FullFS = "+invariant-function-descriptors," + FullFS;
202     else
203       FullFS = "+invariant-function-descriptors";
204   }
205 
206   if (TT.isOSAIX()) {
207     if (!FullFS.empty())
208       FullFS = "+aix," + FullFS;
209     else
210       FullFS = "+aix";
211   }
212 
213   return FullFS;
214 }
215 
216 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
217   if (TT.isOSAIX())
218     return std::make_unique<TargetLoweringObjectFileXCOFF>();
219 
220   return std::make_unique<PPC64LinuxTargetObjectFile>();
221 }
222 
223 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
224                                                  const TargetOptions &Options) {
225   if (Options.MCOptions.getABIName().startswith("elfv1"))
226     return PPCTargetMachine::PPC_ABI_ELFv1;
227   else if (Options.MCOptions.getABIName().startswith("elfv2"))
228     return PPCTargetMachine::PPC_ABI_ELFv2;
229 
230   assert(Options.MCOptions.getABIName().empty() &&
231          "Unknown target-abi option!");
232 
233   if (TT.isMacOSX())
234     return PPCTargetMachine::PPC_ABI_UNKNOWN;
235 
236   switch (TT.getArch()) {
237   case Triple::ppc64le:
238     return PPCTargetMachine::PPC_ABI_ELFv2;
239   case Triple::ppc64:
240     return PPCTargetMachine::PPC_ABI_ELFv1;
241   default:
242     return PPCTargetMachine::PPC_ABI_UNKNOWN;
243   }
244 }
245 
246 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
247                                            Optional<Reloc::Model> RM) {
248   assert((!TT.isOSAIX() || !RM.hasValue() || *RM == Reloc::PIC_) &&
249          "Invalid relocation model for AIX.");
250 
251   if (RM.hasValue())
252     return *RM;
253 
254   // Big Endian PPC and AIX default to PIC.
255   if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
256     return Reloc::PIC_;
257 
258   // Rest are static by default.
259   return Reloc::Static;
260 }
261 
262 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
263                                                  Optional<CodeModel::Model> CM,
264                                                  bool JIT) {
265   if (CM) {
266     if (*CM == CodeModel::Tiny)
267       report_fatal_error("Target does not support the tiny CodeModel", false);
268     if (*CM == CodeModel::Kernel)
269       report_fatal_error("Target does not support the kernel CodeModel", false);
270     return *CM;
271   }
272 
273   if (JIT)
274     return CodeModel::Small;
275   if (TT.isOSAIX())
276     return CodeModel::Small;
277 
278   assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
279 
280   if (TT.isArch32Bit())
281     return CodeModel::Small;
282 
283   assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
284   return CodeModel::Medium;
285 }
286 
287 
288 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
289   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
290   ScheduleDAGMILive *DAG =
291     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
292                           std::make_unique<PPCPreRASchedStrategy>(C) :
293                           std::make_unique<GenericScheduler>(C));
294   // add DAG Mutations here.
295   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
296   if (ST.hasStoreFusion())
297     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
298   if (ST.hasFusion())
299     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
300 
301   return DAG;
302 }
303 
304 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
305   MachineSchedContext *C) {
306   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
307   ScheduleDAGMI *DAG =
308     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
309                       std::make_unique<PPCPostRASchedStrategy>(C) :
310                       std::make_unique<PostGenericScheduler>(C), true);
311   // add DAG Mutations here.
312   if (ST.hasStoreFusion())
313     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
314   if (ST.hasFusion())
315     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
316   return DAG;
317 }
318 
319 // The FeatureString here is a little subtle. We are modifying the feature
320 // string with what are (currently) non-function specific overrides as it goes
321 // into the LLVMTargetMachine constructor and then using the stored value in the
322 // Subtarget constructor below it.
323 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
324                                    StringRef CPU, StringRef FS,
325                                    const TargetOptions &Options,
326                                    Optional<Reloc::Model> RM,
327                                    Optional<CodeModel::Model> CM,
328                                    CodeGenOpt::Level OL, bool JIT)
329     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
330                         computeFSAdditions(FS, OL, TT), Options,
331                         getEffectiveRelocModel(TT, RM),
332                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
333       TLOF(createTLOF(getTargetTriple())),
334       TargetABI(computeTargetABI(TT, Options)),
335       Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
336   initAsmInfo();
337 }
338 
339 PPCTargetMachine::~PPCTargetMachine() = default;
340 
341 const PPCSubtarget *
342 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
343   Attribute CPUAttr = F.getFnAttribute("target-cpu");
344   Attribute FSAttr = F.getFnAttribute("target-features");
345 
346   std::string CPU =
347       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
348   std::string FS =
349       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
350 
351   // FIXME: This is related to the code below to reset the target options,
352   // we need to know whether or not the soft float flag is set on the
353   // function before we can generate a subtarget. We also need to use
354   // it as a key for the subtarget since that can be the only difference
355   // between two functions.
356   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
357   // If the soft float attribute is set on the function turn on the soft float
358   // subtarget feature.
359   if (SoftFloat)
360     FS += FS.empty() ? "-hard-float" : ",-hard-float";
361 
362   auto &I = SubtargetMap[CPU + FS];
363   if (!I) {
364     // This needs to be done before we create a new subtarget since any
365     // creation will depend on the TM and the code generation flags on the
366     // function that reside in TargetOptions.
367     resetTargetOptions(F);
368     I = std::make_unique<PPCSubtarget>(
369         TargetTriple, CPU,
370         // FIXME: It would be good to have the subtarget additions here
371         // not necessary. Anything that turns them on/off (overrides) ends
372         // up being put at the end of the feature string, but the defaults
373         // shouldn't require adding them. Fixing this means pulling Feature64Bit
374         // out of most of the target cpus in the .td file and making it set only
375         // as part of initialization via the TargetTriple.
376         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
377   }
378   return I.get();
379 }
380 
381 //===----------------------------------------------------------------------===//
382 // Pass Pipeline Configuration
383 //===----------------------------------------------------------------------===//
384 
385 namespace {
386 
387 /// PPC Code Generator Pass Configuration Options.
388 class PPCPassConfig : public TargetPassConfig {
389 public:
390   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
391     : TargetPassConfig(TM, PM) {
392     // At any optimization level above -O0 we use the Machine Scheduler and not
393     // the default Post RA List Scheduler.
394     if (TM.getOptLevel() != CodeGenOpt::None)
395       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
396   }
397 
398   PPCTargetMachine &getPPCTargetMachine() const {
399     return getTM<PPCTargetMachine>();
400   }
401 
402   void addIRPasses() override;
403   bool addPreISel() override;
404   bool addILPOpts() override;
405   bool addInstSelector() override;
406   void addMachineSSAOptimization() override;
407   void addPreRegAlloc() override;
408   void addPreSched2() override;
409   void addPreEmitPass() override;
410   void addPreEmitPass2() override;
411   // GlobalISEL
412   bool addIRTranslator() override;
413   bool addLegalizeMachineIR() override;
414   bool addRegBankSelect() override;
415   bool addGlobalInstructionSelect() override;
416 
417   ScheduleDAGInstrs *
418   createMachineScheduler(MachineSchedContext *C) const override {
419     return createPPCMachineScheduler(C);
420   }
421   ScheduleDAGInstrs *
422   createPostMachineScheduler(MachineSchedContext *C) const override {
423     return createPPCPostMachineScheduler(C);
424   }
425 };
426 
427 } // end anonymous namespace
428 
429 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
430   return new PPCPassConfig(*this, PM);
431 }
432 
433 void PPCPassConfig::addIRPasses() {
434   if (TM->getOptLevel() != CodeGenOpt::None)
435     addPass(createPPCBoolRetToIntPass());
436   addPass(createAtomicExpandPass());
437 
438   // Lower generic MASSV routines to PowerPC subtarget-specific entries.
439   addPass(createPPCLowerMASSVEntriesPass());
440 
441   // Generate PowerPC target-specific entries for scalar math functions
442   // that are available in IBM MASS (scalar) library.
443   if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
444       EnablePPCGenScalarMASSEntries) {
445     TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
446     addPass(createPPCGenScalarMASSEntriesPass());
447   }
448 
449   // If explicitly requested, add explicit data prefetch intrinsics.
450   if (EnablePrefetch.getNumOccurrences() > 0)
451     addPass(createLoopDataPrefetchPass());
452 
453   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
454     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
455     // and lower a GEP with multiple indices to either arithmetic operations or
456     // multiple GEPs with single index.
457     addPass(createSeparateConstOffsetFromGEPPass(true));
458     // Call EarlyCSE pass to find and remove subexpressions in the lowered
459     // result.
460     addPass(createEarlyCSEPass());
461     // Do loop invariant code motion in case part of the lowered result is
462     // invariant.
463     addPass(createLICMPass());
464   }
465 
466   TargetPassConfig::addIRPasses();
467 }
468 
469 bool PPCPassConfig::addPreISel() {
470   if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
471     addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
472 
473   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
474     addPass(createHardwareLoopsPass());
475 
476   return false;
477 }
478 
479 bool PPCPassConfig::addILPOpts() {
480   addPass(&EarlyIfConverterID);
481 
482   if (EnableMachineCombinerPass)
483     addPass(&MachineCombinerID);
484 
485   return true;
486 }
487 
488 bool PPCPassConfig::addInstSelector() {
489   // Install an instruction selector.
490   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
491 
492 #ifndef NDEBUG
493   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
494     addPass(createPPCCTRLoopsVerify());
495 #endif
496 
497   addPass(createPPCVSXCopyPass());
498   return false;
499 }
500 
501 void PPCPassConfig::addMachineSSAOptimization() {
502   // PPCBranchCoalescingPass need to be done before machine sinking
503   // since it merges empty blocks.
504   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
505     addPass(createPPCBranchCoalescingPass());
506   TargetPassConfig::addMachineSSAOptimization();
507   // For little endian, remove where possible the vector swap instructions
508   // introduced at code generation to normalize vector element order.
509   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
510       !DisableVSXSwapRemoval)
511     addPass(createPPCVSXSwapRemovalPass());
512   // Reduce the number of cr-logical ops.
513   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
514     addPass(createPPCReduceCRLogicalsPass());
515   // Target-specific peephole cleanups performed after instruction
516   // selection.
517   if (!DisableMIPeephole) {
518     addPass(createPPCMIPeepholePass());
519     addPass(&DeadMachineInstructionElimID);
520   }
521 }
522 
523 void PPCPassConfig::addPreRegAlloc() {
524   if (getOptLevel() != CodeGenOpt::None) {
525     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
526     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
527                &PPCVSXFMAMutateID);
528   }
529 
530   // FIXME: We probably don't need to run these for -fPIE.
531   if (getPPCTargetMachine().isPositionIndependent()) {
532     // FIXME: LiveVariables should not be necessary here!
533     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
534     // LiveVariables. This (unnecessary) dependency has been removed now,
535     // however a stage-2 clang build fails without LiveVariables computed here.
536     addPass(&LiveVariablesID);
537     addPass(createPPCTLSDynamicCallPass());
538   }
539   if (EnableExtraTOCRegDeps)
540     addPass(createPPCTOCRegDepsPass());
541 
542   if (getOptLevel() != CodeGenOpt::None)
543     addPass(&MachinePipelinerID);
544 }
545 
546 void PPCPassConfig::addPreSched2() {
547   if (getOptLevel() != CodeGenOpt::None)
548     addPass(&IfConverterID);
549 }
550 
551 void PPCPassConfig::addPreEmitPass() {
552   addPass(createPPCPreEmitPeepholePass());
553   addPass(createPPCExpandISELPass());
554 
555   if (getOptLevel() != CodeGenOpt::None)
556     addPass(createPPCEarlyReturnPass());
557 }
558 
559 void PPCPassConfig::addPreEmitPass2() {
560   // Schedule the expansion of AMOs at the last possible moment, avoiding the
561   // possibility for other passes to break the requirements for forward
562   // progress in the LL/SC block.
563   addPass(createPPCExpandAtomicPseudoPass());
564   // Must run branch selection immediately preceding the asm printer.
565   addPass(createPPCBranchSelectionPass());
566 }
567 
568 TargetTransformInfo
569 PPCTargetMachine::getTargetTransformInfo(const Function &F) const {
570   return TargetTransformInfo(PPCTTIImpl(this, F));
571 }
572 
573 bool PPCTargetMachine::isLittleEndian() const {
574   assert(Endianness != Endian::NOT_DETECTED &&
575          "Unable to determine endianness");
576   return Endianness == Endian::LITTLE;
577 }
578 
579 static MachineSchedRegistry
580 PPCPreRASchedRegistry("ppc-prera",
581                       "Run PowerPC PreRA specific scheduler",
582                       createPPCMachineScheduler);
583 
584 static MachineSchedRegistry
585 PPCPostRASchedRegistry("ppc-postra",
586                        "Run PowerPC PostRA specific scheduler",
587                        createPPCPostMachineScheduler);
588 
589 // Global ISEL
590 bool PPCPassConfig::addIRTranslator() {
591   addPass(new IRTranslator());
592   return false;
593 }
594 
595 bool PPCPassConfig::addLegalizeMachineIR() {
596   addPass(new Legalizer());
597   return false;
598 }
599 
600 bool PPCPassConfig::addRegBankSelect() {
601   addPass(new RegBankSelect());
602   return false;
603 }
604 
605 bool PPCPassConfig::addGlobalInstructionSelect() {
606   addPass(new InstructionSelect(getOptLevel()));
607   return false;
608 }
609