1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 static cl::
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                         cl::desc("Disable CTR loops for PPC"));
28 
29 extern "C" void LLVMInitializePowerPCTarget() {
30   // Register the targets
31   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
34 }
35 
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38   const Triple &T = ST.getTargetTriple();
39 
40   // PPC is big endian.
41   std::string Ret = "E";
42 
43   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
44   // pointers.
45   if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
46     Ret += "-p:32:32";
47 
48   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
49   // documentation are wrong; these are correct (i.e. "what gcc does").
50   if (ST.isPPC64() || ST.isSVR4ABI())
51     Ret += "-i64:64";
52   else
53     Ret += "-f64:32:64";
54 
55   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
56   if (ST.isPPC64())
57     Ret += "-n32:64";
58   else
59     Ret += "-n32";
60 
61   return Ret;
62 }
63 
64 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
65                                    StringRef CPU, StringRef FS,
66                                    const TargetOptions &Options,
67                                    Reloc::Model RM, CodeModel::Model CM,
68                                    CodeGenOpt::Level OL,
69                                    bool is64Bit)
70   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
71     Subtarget(TT, CPU, FS, is64Bit),
72     DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
73     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
74     TLInfo(*this), TSInfo(*this),
75     InstrItins(Subtarget.getInstrItineraryData()) {
76 
77   // The binutils for the BG/P are too old for CFI.
78   if (Subtarget.isBGP())
79     setMCUseCFI(false);
80   initAsmInfo();
81 }
82 
83 void PPC32TargetMachine::anchor() { }
84 
85 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
86                                        StringRef CPU, StringRef FS,
87                                        const TargetOptions &Options,
88                                        Reloc::Model RM, CodeModel::Model CM,
89                                        CodeGenOpt::Level OL)
90   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
91 }
92 
93 void PPC64TargetMachine::anchor() { }
94 
95 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
96                                        StringRef CPU,  StringRef FS,
97                                        const TargetOptions &Options,
98                                        Reloc::Model RM, CodeModel::Model CM,
99                                        CodeGenOpt::Level OL)
100   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
101 }
102 
103 
104 //===----------------------------------------------------------------------===//
105 // Pass Pipeline Configuration
106 //===----------------------------------------------------------------------===//
107 
108 namespace {
109 /// PPC Code Generator Pass Configuration Options.
110 class PPCPassConfig : public TargetPassConfig {
111 public:
112   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
113     : TargetPassConfig(TM, PM) {}
114 
115   PPCTargetMachine &getPPCTargetMachine() const {
116     return getTM<PPCTargetMachine>();
117   }
118 
119   const PPCSubtarget &getPPCSubtarget() const {
120     return *getPPCTargetMachine().getSubtargetImpl();
121   }
122 
123   virtual bool addPreISel();
124   virtual bool addILPOpts();
125   virtual bool addInstSelector();
126   virtual bool addPreSched2();
127   virtual bool addPreEmitPass();
128 };
129 } // namespace
130 
131 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
132   return new PPCPassConfig(this, PM);
133 }
134 
135 bool PPCPassConfig::addPreISel() {
136   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
137     addPass(createPPCCTRLoops(getPPCTargetMachine()));
138 
139   return false;
140 }
141 
142 bool PPCPassConfig::addILPOpts() {
143   if (getPPCSubtarget().hasISEL()) {
144     addPass(&EarlyIfConverterID);
145     return true;
146   }
147 
148   return false;
149 }
150 
151 bool PPCPassConfig::addInstSelector() {
152   // Install an instruction selector.
153   addPass(createPPCISelDag(getPPCTargetMachine()));
154 
155 #ifndef NDEBUG
156   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
157     addPass(createPPCCTRLoopsVerify());
158 #endif
159 
160   return false;
161 }
162 
163 bool PPCPassConfig::addPreSched2() {
164   if (getOptLevel() != CodeGenOpt::None)
165     addPass(&IfConverterID);
166 
167   return true;
168 }
169 
170 bool PPCPassConfig::addPreEmitPass() {
171   if (getOptLevel() != CodeGenOpt::None)
172     addPass(createPPCEarlyReturnPass());
173   // Must run branch selection immediately preceding the asm printer.
174   addPass(createPPCBranchSelectionPass());
175   return false;
176 }
177 
178 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
179                                       JITCodeEmitter &JCE) {
180   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
181   // writing?
182   Subtarget.SetJITMode();
183 
184   // Machine code emitter pass for PowerPC.
185   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
186 
187   return false;
188 }
189 
190 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
191   // Add first the target-independent BasicTTI pass, then our PPC pass. This
192   // allows the PPC pass to delegate to the target independent layer when
193   // appropriate.
194   PM.add(createBasicTargetTransformInfoPass(this));
195   PM.add(createPPCTargetTransformInfoPass(this));
196 }
197 
198