1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31                         cl::desc("Disable CTR loops for PPC"));
32 
33 static cl::
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35                             cl::desc("Disable PPC loop preinc prep"));
36 
37 static cl::opt<bool>
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
40 
41 static cl::
42 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
43                                 cl::desc("Disable VSX Swap Removal for PPC"));
44 
45 static cl::opt<bool>
46 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
47              cl::desc("Enable optimizations on complex GEPs"),
48              cl::init(true));
49 
50 static cl::opt<bool>
51 EnablePrefetch("enable-ppc-prefetching",
52                   cl::desc("disable software prefetching on PPC"),
53                   cl::init(false), cl::Hidden);
54 
55 static cl::opt<bool>
56 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
57                       cl::desc("Add extra TOC register dependencies"),
58                       cl::init(true), cl::Hidden);
59 
60 extern "C" void LLVMInitializePowerPCTarget() {
61   // Register the targets
62   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
63   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
64   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
65 }
66 
67 /// Return the datalayout string of a subtarget.
68 static std::string getDataLayoutString(const Triple &T) {
69   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
70   std::string Ret;
71 
72   // Most PPC* platforms are big endian, PPC64LE is little endian.
73   if (T.getArch() == Triple::ppc64le)
74     Ret = "e";
75   else
76     Ret = "E";
77 
78   Ret += DataLayout::getManglingComponent(T);
79 
80   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
81   // pointers.
82   if (!is64Bit || T.getOS() == Triple::Lv2)
83     Ret += "-p:32:32";
84 
85   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
86   // documentation are wrong; these are correct (i.e. "what gcc does").
87   if (is64Bit || !T.isOSDarwin())
88     Ret += "-i64:64";
89   else
90     Ret += "-f64:32:64";
91 
92   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
93   if (is64Bit)
94     Ret += "-n32:64";
95   else
96     Ret += "-n32";
97 
98   return Ret;
99 }
100 
101 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
102   std::string FullFS = FS;
103   Triple TargetTriple(TT);
104 
105   // Make sure 64-bit features are available when CPUname is generic
106   if (TargetTriple.getArch() == Triple::ppc64 ||
107       TargetTriple.getArch() == Triple::ppc64le) {
108     if (!FullFS.empty())
109       FullFS = "+64bit," + FullFS;
110     else
111       FullFS = "+64bit";
112   }
113 
114   if (OL >= CodeGenOpt::Default) {
115     if (!FullFS.empty())
116       FullFS = "+crbits," + FullFS;
117     else
118       FullFS = "+crbits";
119   }
120 
121   if (OL != CodeGenOpt::None) {
122      if (!FullFS.empty())
123       FullFS = "+invariant-function-descriptors," + FullFS;
124     else
125       FullFS = "+invariant-function-descriptors";
126   }
127 
128   return FullFS;
129 }
130 
131 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
132   // If it isn't a Mach-O file then it's going to be a linux ELF
133   // object file.
134   if (TT.isOSDarwin())
135     return make_unique<TargetLoweringObjectFileMachO>();
136 
137   return make_unique<PPC64LinuxTargetObjectFile>();
138 }
139 
140 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
141                                                  const TargetOptions &Options) {
142   if (Options.MCOptions.getABIName().startswith("elfv1"))
143     return PPCTargetMachine::PPC_ABI_ELFv1;
144   else if (Options.MCOptions.getABIName().startswith("elfv2"))
145     return PPCTargetMachine::PPC_ABI_ELFv2;
146 
147   assert(Options.MCOptions.getABIName().empty() &&
148 	 "Unknown target-abi option!");
149 
150   if (!TT.isMacOSX()) {
151     switch (TT.getArch()) {
152     case Triple::ppc64le:
153       return PPCTargetMachine::PPC_ABI_ELFv2;
154     case Triple::ppc64:
155       return PPCTargetMachine::PPC_ABI_ELFv1;
156     default:
157       // Fallthrough.
158       ;
159     }
160   }
161   return PPCTargetMachine::PPC_ABI_UNKNOWN;
162 }
163 
164 // The FeatureString here is a little subtle. We are modifying the feature string
165 // with what are (currently) non-function specific overrides as it goes into the
166 // LLVMTargetMachine constructor and then using the stored value in the
167 // Subtarget constructor below it.
168 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
169                                    StringRef FS, const TargetOptions &Options,
170                                    Reloc::Model RM, CodeModel::Model CM,
171                                    CodeGenOpt::Level OL)
172     : LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
173                         computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
174       TLOF(createTLOF(Triple(getTargetTriple()))),
175       TargetABI(computeTargetABI(Triple(TT), Options)) {
176   initAsmInfo();
177 }
178 
179 PPCTargetMachine::~PPCTargetMachine() {}
180 
181 void PPC32TargetMachine::anchor() { }
182 
183 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
184                                        StringRef CPU, StringRef FS,
185                                        const TargetOptions &Options,
186                                        Reloc::Model RM, CodeModel::Model CM,
187                                        CodeGenOpt::Level OL)
188   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
189 }
190 
191 void PPC64TargetMachine::anchor() { }
192 
193 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
194                                        StringRef CPU,  StringRef FS,
195                                        const TargetOptions &Options,
196                                        Reloc::Model RM, CodeModel::Model CM,
197                                        CodeGenOpt::Level OL)
198   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
199 }
200 
201 const PPCSubtarget *
202 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
203   Attribute CPUAttr = F.getFnAttribute("target-cpu");
204   Attribute FSAttr = F.getFnAttribute("target-features");
205 
206   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
207                         ? CPUAttr.getValueAsString().str()
208                         : TargetCPU;
209   std::string FS = !FSAttr.hasAttribute(Attribute::None)
210                        ? FSAttr.getValueAsString().str()
211                        : TargetFS;
212 
213   auto &I = SubtargetMap[CPU + FS];
214   if (!I) {
215     // This needs to be done before we create a new subtarget since any
216     // creation will depend on the TM and the code generation flags on the
217     // function that reside in TargetOptions.
218     resetTargetOptions(F);
219     I = llvm::make_unique<PPCSubtarget>(
220         TargetTriple, CPU,
221         // FIXME: It would be good to have the subtarget additions here
222         // not necessary. Anything that turns them on/off (overrides) ends
223         // up being put at the end of the feature string, but the defaults
224         // shouldn't require adding them. Fixing this means pulling Feature64Bit
225         // out of most of the target cpus in the .td file and making it set only
226         // as part of initialization via the TargetTriple.
227         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
228   }
229   return I.get();
230 }
231 
232 //===----------------------------------------------------------------------===//
233 // Pass Pipeline Configuration
234 //===----------------------------------------------------------------------===//
235 
236 namespace {
237 /// PPC Code Generator Pass Configuration Options.
238 class PPCPassConfig : public TargetPassConfig {
239 public:
240   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
241     : TargetPassConfig(TM, PM) {}
242 
243   PPCTargetMachine &getPPCTargetMachine() const {
244     return getTM<PPCTargetMachine>();
245   }
246 
247   void addIRPasses() override;
248   bool addPreISel() override;
249   bool addILPOpts() override;
250   bool addInstSelector() override;
251   void addMachineSSAOptimization() override;
252   void addPreRegAlloc() override;
253   void addPreSched2() override;
254   void addPreEmitPass() override;
255 };
256 } // namespace
257 
258 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
259   return new PPCPassConfig(this, PM);
260 }
261 
262 void PPCPassConfig::addIRPasses() {
263   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
264 
265   // For the BG/Q (or if explicitly requested), add explicit data prefetch
266   // intrinsics.
267   bool UsePrefetching =
268     Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&
269     getOptLevel() != CodeGenOpt::None;
270   if (EnablePrefetch.getNumOccurrences() > 0)
271     UsePrefetching = EnablePrefetch;
272   if (UsePrefetching)
273     addPass(createPPCLoopDataPrefetchPass());
274 
275   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
276     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
277     // and lower a GEP with multiple indices to either arithmetic operations or
278     // multiple GEPs with single index.
279     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
280     // Call EarlyCSE pass to find and remove subexpressions in the lowered
281     // result.
282     addPass(createEarlyCSEPass());
283     // Do loop invariant code motion in case part of the lowered result is
284     // invariant.
285     addPass(createLICMPass());
286   }
287 
288   TargetPassConfig::addIRPasses();
289 }
290 
291 bool PPCPassConfig::addPreISel() {
292   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
293     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
294 
295   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
296     addPass(createPPCCTRLoops(getPPCTargetMachine()));
297 
298   return false;
299 }
300 
301 bool PPCPassConfig::addILPOpts() {
302   addPass(&EarlyIfConverterID);
303   return true;
304 }
305 
306 bool PPCPassConfig::addInstSelector() {
307   // Install an instruction selector.
308   addPass(createPPCISelDag(getPPCTargetMachine()));
309 
310 #ifndef NDEBUG
311   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
312     addPass(createPPCCTRLoopsVerify());
313 #endif
314 
315   addPass(createPPCVSXCopyPass());
316   return false;
317 }
318 
319 void PPCPassConfig::addMachineSSAOptimization() {
320   TargetPassConfig::addMachineSSAOptimization();
321   // For little endian, remove where possible the vector swap instructions
322   // introduced at code generation to normalize vector element order.
323   if (Triple(TM->getTargetTriple()).getArch() == Triple::ppc64le &&
324       !DisableVSXSwapRemoval)
325     addPass(createPPCVSXSwapRemovalPass());
326 }
327 
328 void PPCPassConfig::addPreRegAlloc() {
329   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
330   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
331              &PPCVSXFMAMutateID);
332   if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
333     addPass(createPPCTLSDynamicCallPass());
334   if (EnableExtraTOCRegDeps)
335     addPass(createPPCTOCRegDepsPass());
336 }
337 
338 void PPCPassConfig::addPreSched2() {
339   if (getOptLevel() != CodeGenOpt::None)
340     addPass(&IfConverterID);
341 }
342 
343 void PPCPassConfig::addPreEmitPass() {
344   if (getOptLevel() != CodeGenOpt::None)
345     addPass(createPPCEarlyReturnPass(), false);
346   // Must run branch selection immediately preceding the asm printer.
347   addPass(createPPCBranchSelectionPass(), false);
348 }
349 
350 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
351   return TargetIRAnalysis(
352       [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
353 }
354