1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31                         cl::desc("Disable CTR loops for PPC"));
32 
33 static cl::
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35                             cl::desc("Disable PPC loop preinc prep"));
36 
37 static cl::opt<bool>
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
40 
41 static cl::
42 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
43                                 cl::desc("Disable VSX Swap Removal for PPC"));
44 
45 static cl::opt<bool>
46 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
47              cl::desc("Enable optimizations on complex GEPs"),
48              cl::init(true));
49 
50 static cl::opt<bool>
51 EnablePrefetch("enable-ppc-prefetching",
52                   cl::desc("disable software prefetching on PPC"),
53                   cl::init(false), cl::Hidden);
54 
55 static cl::opt<bool>
56 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
57                       cl::desc("Add extra TOC register dependencies"),
58                       cl::init(true), cl::Hidden);
59 
60 static cl::opt<bool>
61 EnableMachineCombinerPass("ppc-machine-combiner",
62                           cl::desc("Enable the machine combiner pass"),
63                           cl::init(true), cl::Hidden);
64 
65 extern "C" void LLVMInitializePowerPCTarget() {
66   // Register the targets
67   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
68   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
69   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
70 }
71 
72 /// Return the datalayout string of a subtarget.
73 static std::string getDataLayoutString(const Triple &T) {
74   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
75   std::string Ret;
76 
77   // Most PPC* platforms are big endian, PPC64LE is little endian.
78   if (T.getArch() == Triple::ppc64le)
79     Ret = "e";
80   else
81     Ret = "E";
82 
83   Ret += DataLayout::getManglingComponent(T);
84 
85   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
86   // pointers.
87   if (!is64Bit || T.getOS() == Triple::Lv2)
88     Ret += "-p:32:32";
89 
90   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
91   // documentation are wrong; these are correct (i.e. "what gcc does").
92   if (is64Bit || !T.isOSDarwin())
93     Ret += "-i64:64";
94   else
95     Ret += "-f64:32:64";
96 
97   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
98   if (is64Bit)
99     Ret += "-n32:64";
100   else
101     Ret += "-n32";
102 
103   return Ret;
104 }
105 
106 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
107                                       const Triple &TT) {
108   std::string FullFS = FS;
109 
110   // Make sure 64-bit features are available when CPUname is generic
111   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
112     if (!FullFS.empty())
113       FullFS = "+64bit," + FullFS;
114     else
115       FullFS = "+64bit";
116   }
117 
118   if (OL >= CodeGenOpt::Default) {
119     if (!FullFS.empty())
120       FullFS = "+crbits," + FullFS;
121     else
122       FullFS = "+crbits";
123   }
124 
125   if (OL != CodeGenOpt::None) {
126     if (!FullFS.empty())
127       FullFS = "+invariant-function-descriptors," + FullFS;
128     else
129       FullFS = "+invariant-function-descriptors";
130   }
131 
132   return FullFS;
133 }
134 
135 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
136   // If it isn't a Mach-O file then it's going to be a linux ELF
137   // object file.
138   if (TT.isOSDarwin())
139     return make_unique<TargetLoweringObjectFileMachO>();
140 
141   return make_unique<PPC64LinuxTargetObjectFile>();
142 }
143 
144 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
145                                                  const TargetOptions &Options) {
146   if (Options.MCOptions.getABIName().startswith("elfv1"))
147     return PPCTargetMachine::PPC_ABI_ELFv1;
148   else if (Options.MCOptions.getABIName().startswith("elfv2"))
149     return PPCTargetMachine::PPC_ABI_ELFv2;
150 
151   assert(Options.MCOptions.getABIName().empty() &&
152          "Unknown target-abi option!");
153 
154   if (!TT.isMacOSX()) {
155     switch (TT.getArch()) {
156     case Triple::ppc64le:
157       return PPCTargetMachine::PPC_ABI_ELFv2;
158     case Triple::ppc64:
159       return PPCTargetMachine::PPC_ABI_ELFv1;
160     default:
161       // Fallthrough.
162       ;
163     }
164   }
165   return PPCTargetMachine::PPC_ABI_UNKNOWN;
166 }
167 
168 // The FeatureString here is a little subtle. We are modifying the feature
169 // string with what are (currently) non-function specific overrides as it goes
170 // into the LLVMTargetMachine constructor and then using the stored value in the
171 // Subtarget constructor below it.
172 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
173                                    StringRef CPU, StringRef FS,
174                                    const TargetOptions &Options,
175                                    Reloc::Model RM, CodeModel::Model CM,
176                                    CodeGenOpt::Level OL)
177     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
178                         computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
179       TLOF(createTLOF(getTargetTriple())),
180       TargetABI(computeTargetABI(TT, Options)),
181       Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) {
182 
183   // For the estimates, convergence is quadratic, so we essentially double the
184   // number of digits correct after every iteration. For both FRE and FRSQRTE,
185   // the minimum architected relative accuracy is 2^-5. When hasRecipPrec(),
186   // this is 2^-14. IEEE float has 23 digits and double has 52 digits.
187   unsigned RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3,
188            RefinementSteps64 = RefinementSteps + 1;
189 
190   this->Options.Reciprocals.setDefaults("sqrtf", true, RefinementSteps);
191   this->Options.Reciprocals.setDefaults("vec-sqrtf", true, RefinementSteps);
192   this->Options.Reciprocals.setDefaults("divf", true, RefinementSteps);
193   this->Options.Reciprocals.setDefaults("vec-divf", true, RefinementSteps);
194 
195   this->Options.Reciprocals.setDefaults("sqrtd", true, RefinementSteps64);
196   this->Options.Reciprocals.setDefaults("vec-sqrtd", true, RefinementSteps64);
197   this->Options.Reciprocals.setDefaults("divd", true, RefinementSteps64);
198   this->Options.Reciprocals.setDefaults("vec-divd", true, RefinementSteps64);
199 
200   initAsmInfo();
201 }
202 
203 PPCTargetMachine::~PPCTargetMachine() {}
204 
205 void PPC32TargetMachine::anchor() { }
206 
207 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
208                                        StringRef CPU, StringRef FS,
209                                        const TargetOptions &Options,
210                                        Reloc::Model RM, CodeModel::Model CM,
211                                        CodeGenOpt::Level OL)
212     : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
213 
214 void PPC64TargetMachine::anchor() { }
215 
216 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
217                                        StringRef CPU, StringRef FS,
218                                        const TargetOptions &Options,
219                                        Reloc::Model RM, CodeModel::Model CM,
220                                        CodeGenOpt::Level OL)
221     : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
222 
223 const PPCSubtarget *
224 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
225   Attribute CPUAttr = F.getFnAttribute("target-cpu");
226   Attribute FSAttr = F.getFnAttribute("target-features");
227 
228   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
229                         ? CPUAttr.getValueAsString().str()
230                         : TargetCPU;
231   std::string FS = !FSAttr.hasAttribute(Attribute::None)
232                        ? FSAttr.getValueAsString().str()
233                        : TargetFS;
234 
235   auto &I = SubtargetMap[CPU + FS];
236   if (!I) {
237     // This needs to be done before we create a new subtarget since any
238     // creation will depend on the TM and the code generation flags on the
239     // function that reside in TargetOptions.
240     resetTargetOptions(F);
241     I = llvm::make_unique<PPCSubtarget>(
242         TargetTriple, CPU,
243         // FIXME: It would be good to have the subtarget additions here
244         // not necessary. Anything that turns them on/off (overrides) ends
245         // up being put at the end of the feature string, but the defaults
246         // shouldn't require adding them. Fixing this means pulling Feature64Bit
247         // out of most of the target cpus in the .td file and making it set only
248         // as part of initialization via the TargetTriple.
249         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
250   }
251   return I.get();
252 }
253 
254 //===----------------------------------------------------------------------===//
255 // Pass Pipeline Configuration
256 //===----------------------------------------------------------------------===//
257 
258 namespace {
259 /// PPC Code Generator Pass Configuration Options.
260 class PPCPassConfig : public TargetPassConfig {
261 public:
262   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
263     : TargetPassConfig(TM, PM) {}
264 
265   PPCTargetMachine &getPPCTargetMachine() const {
266     return getTM<PPCTargetMachine>();
267   }
268 
269   void addIRPasses() override;
270   bool addPreISel() override;
271   bool addILPOpts() override;
272   bool addInstSelector() override;
273   void addMachineSSAOptimization() override;
274   void addPreRegAlloc() override;
275   void addPreSched2() override;
276   void addPreEmitPass() override;
277 };
278 } // namespace
279 
280 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
281   return new PPCPassConfig(this, PM);
282 }
283 
284 void PPCPassConfig::addIRPasses() {
285   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
286 
287   // For the BG/Q (or if explicitly requested), add explicit data prefetch
288   // intrinsics.
289   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
290                         getOptLevel() != CodeGenOpt::None;
291   if (EnablePrefetch.getNumOccurrences() > 0)
292     UsePrefetching = EnablePrefetch;
293   if (UsePrefetching)
294     addPass(createPPCLoopDataPrefetchPass());
295 
296   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
297     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
298     // and lower a GEP with multiple indices to either arithmetic operations or
299     // multiple GEPs with single index.
300     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
301     // Call EarlyCSE pass to find and remove subexpressions in the lowered
302     // result.
303     addPass(createEarlyCSEPass());
304     // Do loop invariant code motion in case part of the lowered result is
305     // invariant.
306     addPass(createLICMPass());
307   }
308 
309   TargetPassConfig::addIRPasses();
310 }
311 
312 bool PPCPassConfig::addPreISel() {
313   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
314     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
315 
316   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
317     addPass(createPPCCTRLoops(getPPCTargetMachine()));
318 
319   return false;
320 }
321 
322 bool PPCPassConfig::addILPOpts() {
323   addPass(&EarlyIfConverterID);
324 
325   if (EnableMachineCombinerPass)
326     addPass(&MachineCombinerID);
327 
328   return true;
329 }
330 
331 bool PPCPassConfig::addInstSelector() {
332   // Install an instruction selector.
333   addPass(createPPCISelDag(getPPCTargetMachine()));
334 
335 #ifndef NDEBUG
336   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
337     addPass(createPPCCTRLoopsVerify());
338 #endif
339 
340   addPass(createPPCVSXCopyPass());
341   return false;
342 }
343 
344 void PPCPassConfig::addMachineSSAOptimization() {
345   TargetPassConfig::addMachineSSAOptimization();
346   // For little endian, remove where possible the vector swap instructions
347   // introduced at code generation to normalize vector element order.
348   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
349       !DisableVSXSwapRemoval)
350     addPass(createPPCVSXSwapRemovalPass());
351 }
352 
353 void PPCPassConfig::addPreRegAlloc() {
354   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
355   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
356              &PPCVSXFMAMutateID);
357   if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
358     addPass(createPPCTLSDynamicCallPass());
359   if (EnableExtraTOCRegDeps)
360     addPass(createPPCTOCRegDepsPass());
361 }
362 
363 void PPCPassConfig::addPreSched2() {
364   if (getOptLevel() != CodeGenOpt::None)
365     addPass(&IfConverterID);
366 }
367 
368 void PPCPassConfig::addPreEmitPass() {
369   if (getOptLevel() != CodeGenOpt::None)
370     addPass(createPPCEarlyReturnPass(), false);
371   // Must run branch selection immediately preceding the asm printer.
372   addPass(createPPCBranchSelectionPass(), false);
373 }
374 
375 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
376   return TargetIRAnalysis([this](const Function &F) {
377     return TargetTransformInfo(PPCTTIImpl(this, F));
378   });
379 }
380