1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 static cl::
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                         cl::desc("Disable CTR loops for PPC"));
28 
29 extern "C" void LLVMInitializePowerPCTarget() {
30   // Register the targets
31   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
34 }
35 
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38   const Triple &T = ST.getTargetTriple();
39 
40   std::string Ret;
41 
42   // Most PPC* platforms are big endian, PPC64LE is little endian.
43   if (ST.isLittleEndian())
44     Ret = "e";
45   else
46     Ret = "E";
47 
48   Ret += DataLayout::getManglingComponent(T);
49 
50   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
51   // pointers.
52   if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
53     Ret += "-p:32:32";
54 
55   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
56   // documentation are wrong; these are correct (i.e. "what gcc does").
57   if (ST.isPPC64() || ST.isSVR4ABI())
58     Ret += "-i64:64";
59   else
60     Ret += "-f64:32:64";
61 
62   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
63   if (ST.isPPC64())
64     Ret += "-n32:64";
65   else
66     Ret += "-n32";
67 
68   return Ret;
69 }
70 
71 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
72                                    StringRef CPU, StringRef FS,
73                                    const TargetOptions &Options,
74                                    Reloc::Model RM, CodeModel::Model CM,
75                                    CodeGenOpt::Level OL,
76                                    bool is64Bit)
77   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
78     Subtarget(TT, CPU, FS, is64Bit, OL),
79     DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
80     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
81     TLInfo(*this), TSInfo(*this),
82     InstrItins(Subtarget.getInstrItineraryData()) {
83   initAsmInfo();
84 }
85 
86 void PPC32TargetMachine::anchor() { }
87 
88 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
89                                        StringRef CPU, StringRef FS,
90                                        const TargetOptions &Options,
91                                        Reloc::Model RM, CodeModel::Model CM,
92                                        CodeGenOpt::Level OL)
93   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
94 }
95 
96 void PPC64TargetMachine::anchor() { }
97 
98 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
99                                        StringRef CPU,  StringRef FS,
100                                        const TargetOptions &Options,
101                                        Reloc::Model RM, CodeModel::Model CM,
102                                        CodeGenOpt::Level OL)
103   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
104 }
105 
106 
107 //===----------------------------------------------------------------------===//
108 // Pass Pipeline Configuration
109 //===----------------------------------------------------------------------===//
110 
111 namespace {
112 /// PPC Code Generator Pass Configuration Options.
113 class PPCPassConfig : public TargetPassConfig {
114 public:
115   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
116     : TargetPassConfig(TM, PM) {}
117 
118   PPCTargetMachine &getPPCTargetMachine() const {
119     return getTM<PPCTargetMachine>();
120   }
121 
122   const PPCSubtarget &getPPCSubtarget() const {
123     return *getPPCTargetMachine().getSubtargetImpl();
124   }
125 
126   virtual bool addPreISel();
127   virtual bool addILPOpts();
128   virtual bool addInstSelector();
129   virtual bool addPreSched2();
130   virtual bool addPreEmitPass();
131 };
132 } // namespace
133 
134 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
135   return new PPCPassConfig(this, PM);
136 }
137 
138 bool PPCPassConfig::addPreISel() {
139   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
140     addPass(createPPCCTRLoops(getPPCTargetMachine()));
141 
142   return false;
143 }
144 
145 bool PPCPassConfig::addILPOpts() {
146   if (getPPCSubtarget().hasISEL()) {
147     addPass(&EarlyIfConverterID);
148     return true;
149   }
150 
151   return false;
152 }
153 
154 bool PPCPassConfig::addInstSelector() {
155   // Install an instruction selector.
156   addPass(createPPCISelDag(getPPCTargetMachine()));
157 
158 #ifndef NDEBUG
159   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
160     addPass(createPPCCTRLoopsVerify());
161 #endif
162 
163   addPass(createPPCVSXCopyPass());
164 
165   return false;
166 }
167 
168 bool PPCPassConfig::addPreSched2() {
169   if (getOptLevel() != CodeGenOpt::None)
170     addPass(&IfConverterID);
171 
172   return true;
173 }
174 
175 bool PPCPassConfig::addPreEmitPass() {
176   if (getOptLevel() != CodeGenOpt::None)
177     addPass(createPPCEarlyReturnPass());
178   // Must run branch selection immediately preceding the asm printer.
179   addPass(createPPCBranchSelectionPass());
180   return false;
181 }
182 
183 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
184                                       JITCodeEmitter &JCE) {
185   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
186   // writing?
187   Subtarget.SetJITMode();
188 
189   // Machine code emitter pass for PowerPC.
190   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
191 
192   return false;
193 }
194 
195 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
196   // Add first the target-independent BasicTTI pass, then our PPC pass. This
197   // allows the PPC pass to delegate to the target independent layer when
198   // appropriate.
199   PM.add(createBasicTargetTransformInfoPass(this));
200   PM.add(createPPCTargetTransformInfoPass(this));
201 }
202 
203