1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Transforms/Scalar.h"
26 using namespace llvm;
27 
28 static cl::
29 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
30                         cl::desc("Disable CTR loops for PPC"));
31 
32 static cl::opt<bool>
33 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
34   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
35 
36 static cl::opt<bool>
37 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
38              cl::desc("Enable optimizations on complex GEPs"),
39              cl::init(true));
40 
41 extern "C" void LLVMInitializePowerPCTarget() {
42   // Register the targets
43   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
44   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
45   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
46 }
47 
48 /// Return the datalayout string of a subtarget.
49 static std::string getDataLayoutString(const Triple &T) {
50   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
51   std::string Ret;
52 
53   // Most PPC* platforms are big endian, PPC64LE is little endian.
54   if (T.getArch() == Triple::ppc64le)
55     Ret = "e";
56   else
57     Ret = "E";
58 
59   Ret += DataLayout::getManglingComponent(T);
60 
61   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
62   // pointers.
63   if (!is64Bit || T.getOS() == Triple::Lv2)
64     Ret += "-p:32:32";
65 
66   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
67   // documentation are wrong; these are correct (i.e. "what gcc does").
68   if (is64Bit || !T.isOSDarwin())
69     Ret += "-i64:64";
70   else
71     Ret += "-f64:32:64";
72 
73   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
74   if (is64Bit)
75     Ret += "-n32:64";
76   else
77     Ret += "-n32";
78 
79   return Ret;
80 }
81 
82 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
83   std::string FullFS = FS;
84   Triple TargetTriple(TT);
85 
86   // Make sure 64-bit features are available when CPUname is generic
87   if (TargetTriple.getArch() == Triple::ppc64 ||
88       TargetTriple.getArch() == Triple::ppc64le) {
89     if (!FullFS.empty())
90       FullFS = "+64bit," + FullFS;
91     else
92       FullFS = "+64bit";
93   }
94 
95   if (OL >= CodeGenOpt::Default) {
96     if (!FullFS.empty())
97       FullFS = "+crbits," + FullFS;
98     else
99       FullFS = "+crbits";
100   }
101 
102   if (OL != CodeGenOpt::None) {
103      if (!FullFS.empty())
104       FullFS = "+invariant-function-descriptors," + FullFS;
105     else
106       FullFS = "+invariant-function-descriptors";
107   }
108 
109   return FullFS;
110 }
111 
112 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
113   // If it isn't a Mach-O file then it's going to be a linux ELF
114   // object file.
115   if (TT.isOSDarwin())
116     return make_unique<TargetLoweringObjectFileMachO>();
117 
118   return make_unique<PPC64LinuxTargetObjectFile>();
119 }
120 
121 // The FeatureString here is a little subtle. We are modifying the feature string
122 // with what are (currently) non-function specific overrides as it goes into the
123 // LLVMTargetMachine constructor and then using the stored value in the
124 // Subtarget constructor below it.
125 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
126                                    StringRef FS, const TargetOptions &Options,
127                                    Reloc::Model RM, CodeModel::Model CM,
128                                    CodeGenOpt::Level OL)
129     : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
130                         CM, OL),
131       TLOF(createTLOF(Triple(getTargetTriple()))),
132       DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
133   initAsmInfo();
134 }
135 
136 PPCTargetMachine::~PPCTargetMachine() {}
137 
138 void PPC32TargetMachine::anchor() { }
139 
140 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
141                                        StringRef CPU, StringRef FS,
142                                        const TargetOptions &Options,
143                                        Reloc::Model RM, CodeModel::Model CM,
144                                        CodeGenOpt::Level OL)
145   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
146 }
147 
148 void PPC64TargetMachine::anchor() { }
149 
150 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
151                                        StringRef CPU,  StringRef FS,
152                                        const TargetOptions &Options,
153                                        Reloc::Model RM, CodeModel::Model CM,
154                                        CodeGenOpt::Level OL)
155   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
156 }
157 
158 const PPCSubtarget *
159 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
160   AttributeSet FnAttrs = F.getAttributes();
161   Attribute CPUAttr =
162       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
163   Attribute FSAttr =
164       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
165 
166   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
167                         ? CPUAttr.getValueAsString().str()
168                         : TargetCPU;
169   std::string FS = !FSAttr.hasAttribute(Attribute::None)
170                        ? FSAttr.getValueAsString().str()
171                        : TargetFS;
172 
173   auto &I = SubtargetMap[CPU + FS];
174   if (!I) {
175     // This needs to be done before we create a new subtarget since any
176     // creation will depend on the TM and the code generation flags on the
177     // function that reside in TargetOptions.
178     resetTargetOptions(F);
179     I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
180   }
181   return I.get();
182 }
183 
184 //===----------------------------------------------------------------------===//
185 // Pass Pipeline Configuration
186 //===----------------------------------------------------------------------===//
187 
188 namespace {
189 /// PPC Code Generator Pass Configuration Options.
190 class PPCPassConfig : public TargetPassConfig {
191 public:
192   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
193     : TargetPassConfig(TM, PM) {}
194 
195   PPCTargetMachine &getPPCTargetMachine() const {
196     return getTM<PPCTargetMachine>();
197   }
198 
199   const PPCSubtarget &getPPCSubtarget() const {
200     return *getPPCTargetMachine().getSubtargetImpl();
201   }
202 
203   void addIRPasses() override;
204   bool addPreISel() override;
205   bool addILPOpts() override;
206   bool addInstSelector() override;
207   void addPreRegAlloc() override;
208   void addPreSched2() override;
209   void addPreEmitPass() override;
210 };
211 } // namespace
212 
213 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
214   return new PPCPassConfig(this, PM);
215 }
216 
217 void PPCPassConfig::addIRPasses() {
218   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
219 
220   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
221     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
222     // and lower a GEP with multiple indices to either arithmetic operations or
223     // multiple GEPs with single index.
224     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
225     // Call EarlyCSE pass to find and remove subexpressions in the lowered
226     // result.
227     addPass(createEarlyCSEPass());
228     // Do loop invariant code motion in case part of the lowered result is
229     // invariant.
230     addPass(createLICMPass());
231   }
232 
233   TargetPassConfig::addIRPasses();
234 }
235 
236 bool PPCPassConfig::addPreISel() {
237   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
238     addPass(createPPCCTRLoops(getPPCTargetMachine()));
239 
240   return false;
241 }
242 
243 bool PPCPassConfig::addILPOpts() {
244   addPass(&EarlyIfConverterID);
245   return true;
246 }
247 
248 bool PPCPassConfig::addInstSelector() {
249   // Install an instruction selector.
250   addPass(createPPCISelDag(getPPCTargetMachine()));
251 
252 #ifndef NDEBUG
253   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
254     addPass(createPPCCTRLoopsVerify());
255 #endif
256 
257   addPass(createPPCVSXCopyPass());
258   return false;
259 }
260 
261 void PPCPassConfig::addPreRegAlloc() {
262   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
263   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
264              &PPCVSXFMAMutateID);
265 }
266 
267 void PPCPassConfig::addPreSched2() {
268   addPass(createPPCVSXCopyCleanupPass(), false);
269 
270   if (getOptLevel() != CodeGenOpt::None)
271     addPass(&IfConverterID);
272 }
273 
274 void PPCPassConfig::addPreEmitPass() {
275   if (getOptLevel() != CodeGenOpt::None)
276     addPass(createPPCEarlyReturnPass(), false);
277   // Must run branch selection immediately preceding the asm printer.
278   addPass(createPPCBranchSelectionPass(), false);
279 }
280 
281 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
282   // Add first the target-independent BasicTTI pass, then our PPC pass. This
283   // allows the PPC pass to delegate to the target independent layer when
284   // appropriate.
285   PM.add(createBasicTargetTransformInfoPass(this));
286   PM.add(createPPCTargetTransformInfoPass(this));
287 }
288