1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 static cl::
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                         cl::desc("Disable CTR loops for PPC"));
28 
29 static cl::opt<bool>
30 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
31   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
32 
33 extern "C" void LLVMInitializePowerPCTarget() {
34   // Register the targets
35   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
36   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
37   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
38 }
39 
40 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
41                                    StringRef FS, const TargetOptions &Options,
42                                    Reloc::Model RM, CodeModel::Model CM,
43                                    CodeGenOpt::Level OL)
44     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45       Subtarget(TT, CPU, FS, *this, OL) {
46   initAsmInfo();
47 }
48 
49 void PPC32TargetMachine::anchor() { }
50 
51 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
52                                        StringRef CPU, StringRef FS,
53                                        const TargetOptions &Options,
54                                        Reloc::Model RM, CodeModel::Model CM,
55                                        CodeGenOpt::Level OL)
56   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
57 }
58 
59 void PPC64TargetMachine::anchor() { }
60 
61 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
62                                        StringRef CPU,  StringRef FS,
63                                        const TargetOptions &Options,
64                                        Reloc::Model RM, CodeModel::Model CM,
65                                        CodeGenOpt::Level OL)
66   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
67 }
68 
69 
70 //===----------------------------------------------------------------------===//
71 // Pass Pipeline Configuration
72 //===----------------------------------------------------------------------===//
73 
74 namespace {
75 /// PPC Code Generator Pass Configuration Options.
76 class PPCPassConfig : public TargetPassConfig {
77 public:
78   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
79     : TargetPassConfig(TM, PM) {}
80 
81   PPCTargetMachine &getPPCTargetMachine() const {
82     return getTM<PPCTargetMachine>();
83   }
84 
85   const PPCSubtarget &getPPCSubtarget() const {
86     return *getPPCTargetMachine().getSubtargetImpl();
87   }
88 
89   void addIRPasses() override;
90   bool addPreISel() override;
91   bool addILPOpts() override;
92   bool addInstSelector() override;
93   bool addPreRegAlloc() override;
94   bool addPreSched2() override;
95   bool addPreEmitPass() override;
96 };
97 } // namespace
98 
99 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
100   return new PPCPassConfig(this, PM);
101 }
102 
103 void PPCPassConfig::addIRPasses() {
104   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
105   TargetPassConfig::addIRPasses();
106 }
107 
108 bool PPCPassConfig::addPreISel() {
109   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
110     addPass(createPPCCTRLoops(getPPCTargetMachine()));
111 
112   return false;
113 }
114 
115 bool PPCPassConfig::addILPOpts() {
116   addPass(&EarlyIfConverterID);
117   return true;
118 }
119 
120 bool PPCPassConfig::addInstSelector() {
121   // Install an instruction selector.
122   addPass(createPPCISelDag(getPPCTargetMachine()));
123 
124 #ifndef NDEBUG
125   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
126     addPass(createPPCCTRLoopsVerify());
127 #endif
128 
129   addPass(createPPCVSXCopyPass());
130   return false;
131 }
132 
133 bool PPCPassConfig::addPreRegAlloc() {
134   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
135   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
136              &PPCVSXFMAMutateID);
137   return false;
138 }
139 
140 bool PPCPassConfig::addPreSched2() {
141   addPass(createPPCVSXCopyCleanupPass());
142 
143   if (getOptLevel() != CodeGenOpt::None)
144     addPass(&IfConverterID);
145 
146   return true;
147 }
148 
149 bool PPCPassConfig::addPreEmitPass() {
150   if (getOptLevel() != CodeGenOpt::None)
151     addPass(createPPCEarlyReturnPass());
152   // Must run branch selection immediately preceding the asm printer.
153   addPass(createPPCBranchSelectionPass());
154   return false;
155 }
156 
157 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
158   // Add first the target-independent BasicTTI pass, then our PPC pass. This
159   // allows the PPC pass to delegate to the target independent layer when
160   // appropriate.
161   PM.add(createBasicTargetTransformInfoPass(this));
162   PM.add(createPPCTargetTransformInfoPass(this));
163 }
164 
165