1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPC.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Target/TargetOptions.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 using namespace llvm;
22 
23 extern "C" void LLVMInitializePowerPCTarget() {
24   // Register the targets
25   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
26   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
27 }
28 
29 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
30                                    StringRef CPU, StringRef FS,
31                                    Reloc::Model RM, CodeModel::Model CM,
32                                    CodeGenOpt::Level OL,
33                                    bool is64Bit)
34   : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
35     Subtarget(TT, CPU, FS, is64Bit),
36     DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
37     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
38     TLInfo(*this), TSInfo(*this),
39     InstrItins(Subtarget.getInstrItineraryData()) {
40 }
41 
42 /// Override this for PowerPC.  Tail merging happily breaks up instruction issue
43 /// groups, which typically degrades performance.
44 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
45 
46 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
47                                        StringRef CPU, StringRef FS,
48                                        Reloc::Model RM, CodeModel::Model CM,
49                                        CodeGenOpt::Level OL)
50   : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
51 }
52 
53 
54 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
55                                        StringRef CPU,  StringRef FS,
56                                        Reloc::Model RM, CodeModel::Model CM,
57                                        CodeGenOpt::Level OL)
58   : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
59 }
60 
61 
62 //===----------------------------------------------------------------------===//
63 // Pass Pipeline Configuration
64 //===----------------------------------------------------------------------===//
65 
66 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) {
67   // Install an instruction selector.
68   PM.add(createPPCISelDag(*this));
69   return false;
70 }
71 
72 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) {
73   // Must run branch selection immediately preceding the asm printer.
74   PM.add(createPPCBranchSelectionPass());
75   return false;
76 }
77 
78 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
79                                       JITCodeEmitter &JCE) {
80   // FIXME: This should be moved to TargetJITInfo!!
81   if (Subtarget.isPPC64())
82     // Temporary workaround for the inability of PPC64 JIT to handle jump
83     // tables.
84     DisableJumpTables = true;
85 
86   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
87   // writing?
88   Subtarget.SetJITMode();
89 
90   // Machine code emitter pass for PowerPC.
91   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
92 
93   return false;
94 }
95