1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCMacroFusion.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetObjectFile.h"
20 #include "PPCTargetTransformInfo.h"
21 #include "TargetInfo/PowerPCTargetInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Analysis/TargetTransformInfo.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
30 #include "llvm/CodeGen/GlobalISel/Localizer.h"
31 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
32 #include "llvm/CodeGen/MachineScheduler.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/MC/TargetRegistry.h"
40 #include "llvm/Pass.h"
41 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/Scalar.h"
46 #include <cassert>
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 
53 static cl::opt<bool>
54     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
55                            cl::desc("enable coalescing of duplicate branches for PPC"));
56 static cl::
57 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
58                         cl::desc("Disable CTR loops for PPC"));
59 
60 static cl::
61 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
62                             cl::desc("Disable PPC loop instr form prep"));
63 
64 static cl::opt<bool>
65 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
66   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
67 
68 static cl::
69 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
70                                 cl::desc("Disable VSX Swap Removal for PPC"));
71 
72 static cl::
73 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
74                             cl::desc("Disable machine peepholes for PPC"));
75 
76 static cl::opt<bool>
77 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
78              cl::desc("Enable optimizations on complex GEPs"),
79              cl::init(true));
80 
81 static cl::opt<bool>
82 EnablePrefetch("enable-ppc-prefetching",
83                   cl::desc("enable software prefetching on PPC"),
84                   cl::init(false), cl::Hidden);
85 
86 static cl::opt<bool>
87 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
88                       cl::desc("Add extra TOC register dependencies"),
89                       cl::init(true), cl::Hidden);
90 
91 static cl::opt<bool>
92 EnableMachineCombinerPass("ppc-machine-combiner",
93                           cl::desc("Enable the machine combiner pass"),
94                           cl::init(true), cl::Hidden);
95 
96 static cl::opt<bool>
97   ReduceCRLogical("ppc-reduce-cr-logicals",
98                   cl::desc("Expand eligible cr-logical binary ops to branches"),
99                   cl::init(true), cl::Hidden);
100 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
101   // Register the targets
102   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
103   RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
104   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
105   RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
106 
107   PassRegistry &PR = *PassRegistry::getPassRegistry();
108 #ifndef NDEBUG
109   initializePPCCTRLoopsVerifyPass(PR);
110 #endif
111   initializePPCLoopInstrFormPrepPass(PR);
112   initializePPCTOCRegDepsPass(PR);
113   initializePPCEarlyReturnPass(PR);
114   initializePPCVSXCopyPass(PR);
115   initializePPCVSXFMAMutatePass(PR);
116   initializePPCVSXSwapRemovalPass(PR);
117   initializePPCReduceCRLogicalsPass(PR);
118   initializePPCBSelPass(PR);
119   initializePPCBranchCoalescingPass(PR);
120   initializePPCBoolRetToIntPass(PR);
121   initializePPCExpandISELPass(PR);
122   initializePPCPreEmitPeepholePass(PR);
123   initializePPCTLSDynamicCallPass(PR);
124   initializePPCMIPeepholePass(PR);
125   initializePPCLowerMASSVEntriesPass(PR);
126   initializePPCGenScalarMASSEntriesPass(PR);
127   initializePPCExpandAtomicPseudoPass(PR);
128   initializeGlobalISel(PR);
129 }
130 
131 static bool isLittleEndianTriple(const Triple &T) {
132   return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
133 }
134 
135 /// Return the datalayout string of a subtarget.
136 static std::string getDataLayoutString(const Triple &T) {
137   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
138   std::string Ret;
139 
140   // Most PPC* platforms are big endian, PPC(64)LE is little endian.
141   if (isLittleEndianTriple(T))
142     Ret = "e";
143   else
144     Ret = "E";
145 
146   Ret += DataLayout::getManglingComponent(T);
147 
148   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
149   // pointers.
150   if (!is64Bit || T.getOS() == Triple::Lv2)
151     Ret += "-p:32:32";
152 
153   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
154   // documentation are wrong; these are correct (i.e. "what gcc does").
155   Ret += "-i64:64";
156 
157   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
158   if (is64Bit)
159     Ret += "-n32:64";
160   else
161     Ret += "-n32";
162 
163   // Specify the vector alignment explicitly. For v256i1 and v512i1, the
164   // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
165   // which is 256 and 512 bytes - way over aligned.
166   if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
167     Ret += "-S128-v256:256:256-v512:512:512";
168 
169   return Ret;
170 }
171 
172 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
173                                       const Triple &TT) {
174   std::string FullFS = std::string(FS);
175 
176   // Make sure 64-bit features are available when CPUname is generic
177   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
178     if (!FullFS.empty())
179       FullFS = "+64bit," + FullFS;
180     else
181       FullFS = "+64bit";
182   }
183 
184   if (OL >= CodeGenOpt::Default) {
185     if (!FullFS.empty())
186       FullFS = "+crbits," + FullFS;
187     else
188       FullFS = "+crbits";
189   }
190 
191   if (OL != CodeGenOpt::None) {
192     if (!FullFS.empty())
193       FullFS = "+invariant-function-descriptors," + FullFS;
194     else
195       FullFS = "+invariant-function-descriptors";
196   }
197 
198   if (TT.isOSAIX()) {
199     if (!FullFS.empty())
200       FullFS = "+aix," + FullFS;
201     else
202       FullFS = "+aix";
203   }
204 
205   return FullFS;
206 }
207 
208 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
209   if (TT.isOSAIX())
210     return std::make_unique<TargetLoweringObjectFileXCOFF>();
211 
212   return std::make_unique<PPC64LinuxTargetObjectFile>();
213 }
214 
215 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
216                                                  const TargetOptions &Options) {
217   if (Options.MCOptions.getABIName().startswith("elfv1"))
218     return PPCTargetMachine::PPC_ABI_ELFv1;
219   else if (Options.MCOptions.getABIName().startswith("elfv2"))
220     return PPCTargetMachine::PPC_ABI_ELFv2;
221 
222   assert(Options.MCOptions.getABIName().empty() &&
223          "Unknown target-abi option!");
224 
225   if (TT.isMacOSX())
226     return PPCTargetMachine::PPC_ABI_UNKNOWN;
227 
228   switch (TT.getArch()) {
229   case Triple::ppc64le:
230     return PPCTargetMachine::PPC_ABI_ELFv2;
231   case Triple::ppc64:
232     return PPCTargetMachine::PPC_ABI_ELFv1;
233   default:
234     return PPCTargetMachine::PPC_ABI_UNKNOWN;
235   }
236 }
237 
238 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
239                                            Optional<Reloc::Model> RM) {
240   assert((!TT.isOSAIX() || !RM.hasValue() || *RM == Reloc::PIC_) &&
241          "Invalid relocation model for AIX.");
242 
243   if (RM.hasValue())
244     return *RM;
245 
246   // Big Endian PPC and AIX default to PIC.
247   if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
248     return Reloc::PIC_;
249 
250   // Rest are static by default.
251   return Reloc::Static;
252 }
253 
254 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
255                                                  Optional<CodeModel::Model> CM,
256                                                  bool JIT) {
257   if (CM) {
258     if (*CM == CodeModel::Tiny)
259       report_fatal_error("Target does not support the tiny CodeModel", false);
260     if (*CM == CodeModel::Kernel)
261       report_fatal_error("Target does not support the kernel CodeModel", false);
262     return *CM;
263   }
264 
265   if (JIT)
266     return CodeModel::Small;
267   if (TT.isOSAIX())
268     return CodeModel::Small;
269 
270   assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
271 
272   if (TT.isArch32Bit())
273     return CodeModel::Small;
274 
275   assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
276   return CodeModel::Medium;
277 }
278 
279 
280 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
281   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
282   ScheduleDAGMILive *DAG =
283     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
284                           std::make_unique<PPCPreRASchedStrategy>(C) :
285                           std::make_unique<GenericScheduler>(C));
286   // add DAG Mutations here.
287   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
288   if (ST.hasStoreFusion())
289     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
290   if (ST.hasFusion())
291     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
292 
293   return DAG;
294 }
295 
296 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
297   MachineSchedContext *C) {
298   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
299   ScheduleDAGMI *DAG =
300     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
301                       std::make_unique<PPCPostRASchedStrategy>(C) :
302                       std::make_unique<PostGenericScheduler>(C), true);
303   // add DAG Mutations here.
304   if (ST.hasStoreFusion())
305     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
306   if (ST.hasFusion())
307     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
308   return DAG;
309 }
310 
311 // The FeatureString here is a little subtle. We are modifying the feature
312 // string with what are (currently) non-function specific overrides as it goes
313 // into the LLVMTargetMachine constructor and then using the stored value in the
314 // Subtarget constructor below it.
315 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
316                                    StringRef CPU, StringRef FS,
317                                    const TargetOptions &Options,
318                                    Optional<Reloc::Model> RM,
319                                    Optional<CodeModel::Model> CM,
320                                    CodeGenOpt::Level OL, bool JIT)
321     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
322                         computeFSAdditions(FS, OL, TT), Options,
323                         getEffectiveRelocModel(TT, RM),
324                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
325       TLOF(createTLOF(getTargetTriple())),
326       TargetABI(computeTargetABI(TT, Options)),
327       Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
328   initAsmInfo();
329 }
330 
331 PPCTargetMachine::~PPCTargetMachine() = default;
332 
333 const PPCSubtarget *
334 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
335   Attribute CPUAttr = F.getFnAttribute("target-cpu");
336   Attribute FSAttr = F.getFnAttribute("target-features");
337 
338   std::string CPU =
339       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
340   std::string FS =
341       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
342 
343   // FIXME: This is related to the code below to reset the target options,
344   // we need to know whether or not the soft float flag is set on the
345   // function before we can generate a subtarget. We also need to use
346   // it as a key for the subtarget since that can be the only difference
347   // between two functions.
348   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
349   // If the soft float attribute is set on the function turn on the soft float
350   // subtarget feature.
351   if (SoftFloat)
352     FS += FS.empty() ? "-hard-float" : ",-hard-float";
353 
354   auto &I = SubtargetMap[CPU + FS];
355   if (!I) {
356     // This needs to be done before we create a new subtarget since any
357     // creation will depend on the TM and the code generation flags on the
358     // function that reside in TargetOptions.
359     resetTargetOptions(F);
360     I = std::make_unique<PPCSubtarget>(
361         TargetTriple, CPU,
362         // FIXME: It would be good to have the subtarget additions here
363         // not necessary. Anything that turns them on/off (overrides) ends
364         // up being put at the end of the feature string, but the defaults
365         // shouldn't require adding them. Fixing this means pulling Feature64Bit
366         // out of most of the target cpus in the .td file and making it set only
367         // as part of initialization via the TargetTriple.
368         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
369   }
370   return I.get();
371 }
372 
373 //===----------------------------------------------------------------------===//
374 // Pass Pipeline Configuration
375 //===----------------------------------------------------------------------===//
376 
377 namespace {
378 
379 /// PPC Code Generator Pass Configuration Options.
380 class PPCPassConfig : public TargetPassConfig {
381 public:
382   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
383     : TargetPassConfig(TM, PM) {
384     // At any optimization level above -O0 we use the Machine Scheduler and not
385     // the default Post RA List Scheduler.
386     if (TM.getOptLevel() != CodeGenOpt::None)
387       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
388   }
389 
390   PPCTargetMachine &getPPCTargetMachine() const {
391     return getTM<PPCTargetMachine>();
392   }
393 
394   void addIRPasses() override;
395   bool addPreISel() override;
396   bool addILPOpts() override;
397   bool addInstSelector() override;
398   void addMachineSSAOptimization() override;
399   void addPreRegAlloc() override;
400   void addPreSched2() override;
401   void addPreEmitPass() override;
402   void addPreEmitPass2() override;
403   // GlobalISEL
404   bool addIRTranslator() override;
405   bool addLegalizeMachineIR() override;
406   bool addRegBankSelect() override;
407   bool addGlobalInstructionSelect() override;
408 
409   ScheduleDAGInstrs *
410   createMachineScheduler(MachineSchedContext *C) const override {
411     return createPPCMachineScheduler(C);
412   }
413   ScheduleDAGInstrs *
414   createPostMachineScheduler(MachineSchedContext *C) const override {
415     return createPPCPostMachineScheduler(C);
416   }
417 };
418 
419 } // end anonymous namespace
420 
421 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
422   return new PPCPassConfig(*this, PM);
423 }
424 
425 void PPCPassConfig::addIRPasses() {
426   if (TM->getOptLevel() != CodeGenOpt::None)
427     addPass(createPPCBoolRetToIntPass());
428   addPass(createAtomicExpandPass());
429 
430   // Lower generic MASSV routines to PowerPC subtarget-specific entries.
431   addPass(createPPCLowerMASSVEntriesPass());
432 
433   // Generate PowerPC target-specific entries for scalar math functions
434   // that are available in IBM MASS (scalar) library.
435   if (TM->getOptLevel() == CodeGenOpt::Aggressive) {
436     addPass(createPPCGenScalarMASSEntriesPass());
437   }
438 
439   // If explicitly requested, add explicit data prefetch intrinsics.
440   if (EnablePrefetch.getNumOccurrences() > 0)
441     addPass(createLoopDataPrefetchPass());
442 
443   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
444     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
445     // and lower a GEP with multiple indices to either arithmetic operations or
446     // multiple GEPs with single index.
447     addPass(createSeparateConstOffsetFromGEPPass(true));
448     // Call EarlyCSE pass to find and remove subexpressions in the lowered
449     // result.
450     addPass(createEarlyCSEPass());
451     // Do loop invariant code motion in case part of the lowered result is
452     // invariant.
453     addPass(createLICMPass());
454   }
455 
456   TargetPassConfig::addIRPasses();
457 }
458 
459 bool PPCPassConfig::addPreISel() {
460   if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
461     addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
462 
463   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
464     addPass(createHardwareLoopsPass());
465 
466   return false;
467 }
468 
469 bool PPCPassConfig::addILPOpts() {
470   addPass(&EarlyIfConverterID);
471 
472   if (EnableMachineCombinerPass)
473     addPass(&MachineCombinerID);
474 
475   return true;
476 }
477 
478 bool PPCPassConfig::addInstSelector() {
479   // Install an instruction selector.
480   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
481 
482 #ifndef NDEBUG
483   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
484     addPass(createPPCCTRLoopsVerify());
485 #endif
486 
487   addPass(createPPCVSXCopyPass());
488   return false;
489 }
490 
491 void PPCPassConfig::addMachineSSAOptimization() {
492   // PPCBranchCoalescingPass need to be done before machine sinking
493   // since it merges empty blocks.
494   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
495     addPass(createPPCBranchCoalescingPass());
496   TargetPassConfig::addMachineSSAOptimization();
497   // For little endian, remove where possible the vector swap instructions
498   // introduced at code generation to normalize vector element order.
499   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
500       !DisableVSXSwapRemoval)
501     addPass(createPPCVSXSwapRemovalPass());
502   // Reduce the number of cr-logical ops.
503   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
504     addPass(createPPCReduceCRLogicalsPass());
505   // Target-specific peephole cleanups performed after instruction
506   // selection.
507   if (!DisableMIPeephole) {
508     addPass(createPPCMIPeepholePass());
509     addPass(&DeadMachineInstructionElimID);
510   }
511 }
512 
513 void PPCPassConfig::addPreRegAlloc() {
514   if (getOptLevel() != CodeGenOpt::None) {
515     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
516     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
517                &PPCVSXFMAMutateID);
518   }
519 
520   // FIXME: We probably don't need to run these for -fPIE.
521   if (getPPCTargetMachine().isPositionIndependent()) {
522     // FIXME: LiveVariables should not be necessary here!
523     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
524     // LiveVariables. This (unnecessary) dependency has been removed now,
525     // however a stage-2 clang build fails without LiveVariables computed here.
526     addPass(&LiveVariablesID);
527     addPass(createPPCTLSDynamicCallPass());
528   }
529   if (EnableExtraTOCRegDeps)
530     addPass(createPPCTOCRegDepsPass());
531 
532   if (getOptLevel() != CodeGenOpt::None)
533     addPass(&MachinePipelinerID);
534 }
535 
536 void PPCPassConfig::addPreSched2() {
537   if (getOptLevel() != CodeGenOpt::None)
538     addPass(&IfConverterID);
539 }
540 
541 void PPCPassConfig::addPreEmitPass() {
542   addPass(createPPCPreEmitPeepholePass());
543   addPass(createPPCExpandISELPass());
544 
545   if (getOptLevel() != CodeGenOpt::None)
546     addPass(createPPCEarlyReturnPass());
547 }
548 
549 void PPCPassConfig::addPreEmitPass2() {
550   // Schedule the expansion of AMOs at the last possible moment, avoiding the
551   // possibility for other passes to break the requirements for forward
552   // progress in the LL/SC block.
553   addPass(createPPCExpandAtomicPseudoPass());
554   // Must run branch selection immediately preceding the asm printer.
555   addPass(createPPCBranchSelectionPass());
556 }
557 
558 TargetTransformInfo
559 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
560   return TargetTransformInfo(PPCTTIImpl(this, F));
561 }
562 
563 bool PPCTargetMachine::isLittleEndian() const {
564   assert(Endianness != Endian::NOT_DETECTED &&
565          "Unable to determine endianness");
566   return Endianness == Endian::LITTLE;
567 }
568 
569 static MachineSchedRegistry
570 PPCPreRASchedRegistry("ppc-prera",
571                       "Run PowerPC PreRA specific scheduler",
572                       createPPCMachineScheduler);
573 
574 static MachineSchedRegistry
575 PPCPostRASchedRegistry("ppc-postra",
576                        "Run PowerPC PostRA specific scheduler",
577                        createPPCPostMachineScheduler);
578 
579 // Global ISEL
580 bool PPCPassConfig::addIRTranslator() {
581   addPass(new IRTranslator());
582   return false;
583 }
584 
585 bool PPCPassConfig::addLegalizeMachineIR() {
586   addPass(new Legalizer());
587   return false;
588 }
589 
590 bool PPCPassConfig::addRegBankSelect() {
591   addPass(new RegBankSelect());
592   return false;
593 }
594 
595 bool PPCPassConfig::addGlobalInstructionSelect() {
596   addPass(new InstructionSelect(getOptLevel()));
597   return false;
598 }
599