1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 static cl::
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                         cl::desc("Disable CTR loops for PPC"));
28 
29 extern "C" void LLVMInitializePowerPCTarget() {
30   // Register the targets
31   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
34 }
35 
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38   const Triple &T = ST.getTargetTriple();
39 
40   // PPC is big endian.
41   std::string Ret = "E";
42 
43   // PPC64 has 64 bit pointers, PPC32 has 32 bit pointers.
44   if (ST.isPPC64())
45     Ret += "-p:64:64";
46   else
47     Ret += "-p:32:32";
48 
49   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
50   // documentation are wrong; these are correct (i.e. "what gcc does").
51   Ret += "-f64:64:64-i64:64:64";
52 
53   // Set support for 128 floats depending on the ABI.
54   if (ST.isPPC64() && ST.isSVR4ABI()) {
55     if (T.getOS() != llvm::Triple::FreeBSD)
56       Ret += "-f128:128:128";
57   } else {
58     Ret += "-f128:64:128";
59   }
60 
61   // Some ABIs support 128 bit vectors.
62   if (ST.isPPC64() && ST.isSVR4ABI())
63     Ret += "-v128:128:128";
64 
65   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
66   if (ST.isPPC64())
67     Ret += "-n32:64";
68   else
69     Ret += "-n32";
70 
71   return Ret;
72 }
73 
74 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
75                                    StringRef CPU, StringRef FS,
76                                    const TargetOptions &Options,
77                                    Reloc::Model RM, CodeModel::Model CM,
78                                    CodeGenOpt::Level OL,
79                                    bool is64Bit)
80   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
81     Subtarget(TT, CPU, FS, is64Bit),
82     DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
83     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
84     TLInfo(*this), TSInfo(*this),
85     InstrItins(Subtarget.getInstrItineraryData()) {
86 
87   // The binutils for the BG/P are too old for CFI.
88   if (Subtarget.isBGP())
89     setMCUseCFI(false);
90   initAsmInfo();
91 }
92 
93 void PPC32TargetMachine::anchor() { }
94 
95 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
96                                        StringRef CPU, StringRef FS,
97                                        const TargetOptions &Options,
98                                        Reloc::Model RM, CodeModel::Model CM,
99                                        CodeGenOpt::Level OL)
100   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
101 }
102 
103 void PPC64TargetMachine::anchor() { }
104 
105 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
106                                        StringRef CPU,  StringRef FS,
107                                        const TargetOptions &Options,
108                                        Reloc::Model RM, CodeModel::Model CM,
109                                        CodeGenOpt::Level OL)
110   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
111 }
112 
113 
114 //===----------------------------------------------------------------------===//
115 // Pass Pipeline Configuration
116 //===----------------------------------------------------------------------===//
117 
118 namespace {
119 /// PPC Code Generator Pass Configuration Options.
120 class PPCPassConfig : public TargetPassConfig {
121 public:
122   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
123     : TargetPassConfig(TM, PM) {}
124 
125   PPCTargetMachine &getPPCTargetMachine() const {
126     return getTM<PPCTargetMachine>();
127   }
128 
129   const PPCSubtarget &getPPCSubtarget() const {
130     return *getPPCTargetMachine().getSubtargetImpl();
131   }
132 
133   virtual bool addPreISel();
134   virtual bool addILPOpts();
135   virtual bool addInstSelector();
136   virtual bool addPreSched2();
137   virtual bool addPreEmitPass();
138 };
139 } // namespace
140 
141 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
142   return new PPCPassConfig(this, PM);
143 }
144 
145 bool PPCPassConfig::addPreISel() {
146   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
147     addPass(createPPCCTRLoops(getPPCTargetMachine()));
148 
149   return false;
150 }
151 
152 bool PPCPassConfig::addILPOpts() {
153   if (getPPCSubtarget().hasISEL()) {
154     addPass(&EarlyIfConverterID);
155     return true;
156   }
157 
158   return false;
159 }
160 
161 bool PPCPassConfig::addInstSelector() {
162   // Install an instruction selector.
163   addPass(createPPCISelDag(getPPCTargetMachine()));
164 
165 #ifndef NDEBUG
166   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
167     addPass(createPPCCTRLoopsVerify());
168 #endif
169 
170   return false;
171 }
172 
173 bool PPCPassConfig::addPreSched2() {
174   if (getOptLevel() != CodeGenOpt::None)
175     addPass(&IfConverterID);
176 
177   return true;
178 }
179 
180 bool PPCPassConfig::addPreEmitPass() {
181   if (getOptLevel() != CodeGenOpt::None)
182     addPass(createPPCEarlyReturnPass());
183   // Must run branch selection immediately preceding the asm printer.
184   addPass(createPPCBranchSelectionPass());
185   return false;
186 }
187 
188 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
189                                       JITCodeEmitter &JCE) {
190   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
191   // writing?
192   Subtarget.SetJITMode();
193 
194   // Machine code emitter pass for PowerPC.
195   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
196 
197   return false;
198 }
199 
200 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
201   // Add first the target-independent BasicTTI pass, then our PPC pass. This
202   // allows the PPC pass to delegate to the target independent layer when
203   // appropriate.
204   PM.add(createBasicTargetTransformInfoPass(this));
205   PM.add(createPPCTargetTransformInfoPass(this));
206 }
207 
208