1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31                         cl::desc("Disable CTR loops for PPC"));
32 
33 static cl::
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35                             cl::desc("Disable PPC loop preinc prep"));
36 
37 static cl::opt<bool>
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
40 
41 static cl::
42 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
43                                 cl::desc("Disable VSX Swap Removal for PPC"));
44 
45 static cl::opt<bool>
46 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
47              cl::desc("Enable optimizations on complex GEPs"),
48              cl::init(true));
49 
50 static cl::opt<bool>
51 EnablePrefetch("enable-ppc-prefetching",
52                   cl::desc("disable software prefetching on PPC"),
53                   cl::init(false), cl::Hidden);
54 
55 static cl::opt<bool>
56 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
57                       cl::desc("Add extra TOC register dependencies"),
58                       cl::init(true), cl::Hidden);
59 
60 extern "C" void LLVMInitializePowerPCTarget() {
61   // Register the targets
62   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
63   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
64   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
65 }
66 
67 /// Return the datalayout string of a subtarget.
68 static std::string getDataLayoutString(const Triple &T) {
69   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
70   std::string Ret;
71 
72   // Most PPC* platforms are big endian, PPC64LE is little endian.
73   if (T.getArch() == Triple::ppc64le)
74     Ret = "e";
75   else
76     Ret = "E";
77 
78   Ret += DataLayout::getManglingComponent(T);
79 
80   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
81   // pointers.
82   if (!is64Bit || T.getOS() == Triple::Lv2)
83     Ret += "-p:32:32";
84 
85   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
86   // documentation are wrong; these are correct (i.e. "what gcc does").
87   if (is64Bit || !T.isOSDarwin())
88     Ret += "-i64:64";
89   else
90     Ret += "-f64:32:64";
91 
92   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
93   if (is64Bit)
94     Ret += "-n32:64";
95   else
96     Ret += "-n32";
97 
98   return Ret;
99 }
100 
101 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
102                                       const Triple &TT) {
103   std::string FullFS = FS;
104 
105   // Make sure 64-bit features are available when CPUname is generic
106   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
107     if (!FullFS.empty())
108       FullFS = "+64bit," + FullFS;
109     else
110       FullFS = "+64bit";
111   }
112 
113   if (OL >= CodeGenOpt::Default) {
114     if (!FullFS.empty())
115       FullFS = "+crbits," + FullFS;
116     else
117       FullFS = "+crbits";
118   }
119 
120   if (OL != CodeGenOpt::None) {
121      if (!FullFS.empty())
122       FullFS = "+invariant-function-descriptors," + FullFS;
123     else
124       FullFS = "+invariant-function-descriptors";
125   }
126 
127   return FullFS;
128 }
129 
130 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
131   // If it isn't a Mach-O file then it's going to be a linux ELF
132   // object file.
133   if (TT.isOSDarwin())
134     return make_unique<TargetLoweringObjectFileMachO>();
135 
136   return make_unique<PPC64LinuxTargetObjectFile>();
137 }
138 
139 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
140                                                  const TargetOptions &Options) {
141   if (Options.MCOptions.getABIName().startswith("elfv1"))
142     return PPCTargetMachine::PPC_ABI_ELFv1;
143   else if (Options.MCOptions.getABIName().startswith("elfv2"))
144     return PPCTargetMachine::PPC_ABI_ELFv2;
145 
146   assert(Options.MCOptions.getABIName().empty() &&
147 	 "Unknown target-abi option!");
148 
149   if (!TT.isMacOSX()) {
150     switch (TT.getArch()) {
151     case Triple::ppc64le:
152       return PPCTargetMachine::PPC_ABI_ELFv2;
153     case Triple::ppc64:
154       return PPCTargetMachine::PPC_ABI_ELFv1;
155     default:
156       // Fallthrough.
157       ;
158     }
159   }
160   return PPCTargetMachine::PPC_ABI_UNKNOWN;
161 }
162 
163 // The FeatureString here is a little subtle. We are modifying the feature string
164 // with what are (currently) non-function specific overrides as it goes into the
165 // LLVMTargetMachine constructor and then using the stored value in the
166 // Subtarget constructor below it.
167 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
168                                    StringRef CPU, StringRef FS,
169                                    const TargetOptions &Options,
170                                    Reloc::Model RM, CodeModel::Model CM,
171                                    CodeGenOpt::Level OL)
172     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
173                         computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
174       TLOF(createTLOF(getTargetTriple())),
175       TargetABI(computeTargetABI(TT, Options)),
176       Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) {
177 
178   // For the estimates, convergence is quadratic, so we essentially double the
179   // number of digits correct after every iteration. For both FRE and FRSQRTE,
180   // the minimum architected relative accuracy is 2^-5. When hasRecipPrec(),
181   // this is 2^-14. IEEE float has 23 digits and double has 52 digits.
182   unsigned RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3,
183            RefinementSteps64 = RefinementSteps + 1;
184 
185   this->Options.Reciprocals.setDefaults("sqrtf", true, RefinementSteps);
186   this->Options.Reciprocals.setDefaults("vec-sqrtf", true, RefinementSteps);
187   this->Options.Reciprocals.setDefaults("divf", true, RefinementSteps);
188   this->Options.Reciprocals.setDefaults("vec-divf", true, RefinementSteps);
189 
190   this->Options.Reciprocals.setDefaults("sqrtd", true, RefinementSteps64);
191   this->Options.Reciprocals.setDefaults("vec-sqrtd", true, RefinementSteps64);
192   this->Options.Reciprocals.setDefaults("divd", true, RefinementSteps64);
193   this->Options.Reciprocals.setDefaults("vec-divd", true, RefinementSteps64);
194 
195   initAsmInfo();
196 }
197 
198 PPCTargetMachine::~PPCTargetMachine() {}
199 
200 void PPC32TargetMachine::anchor() { }
201 
202 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
203                                        StringRef CPU, StringRef FS,
204                                        const TargetOptions &Options,
205                                        Reloc::Model RM, CodeModel::Model CM,
206                                        CodeGenOpt::Level OL)
207     : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
208 
209 void PPC64TargetMachine::anchor() { }
210 
211 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
212                                        StringRef CPU, StringRef FS,
213                                        const TargetOptions &Options,
214                                        Reloc::Model RM, CodeModel::Model CM,
215                                        CodeGenOpt::Level OL)
216     : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
217 
218 const PPCSubtarget *
219 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
220   Attribute CPUAttr = F.getFnAttribute("target-cpu");
221   Attribute FSAttr = F.getFnAttribute("target-features");
222 
223   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
224                         ? CPUAttr.getValueAsString().str()
225                         : TargetCPU;
226   std::string FS = !FSAttr.hasAttribute(Attribute::None)
227                        ? FSAttr.getValueAsString().str()
228                        : TargetFS;
229 
230   auto &I = SubtargetMap[CPU + FS];
231   if (!I) {
232     // This needs to be done before we create a new subtarget since any
233     // creation will depend on the TM and the code generation flags on the
234     // function that reside in TargetOptions.
235     resetTargetOptions(F);
236     I = llvm::make_unique<PPCSubtarget>(
237         TargetTriple, CPU,
238         // FIXME: It would be good to have the subtarget additions here
239         // not necessary. Anything that turns them on/off (overrides) ends
240         // up being put at the end of the feature string, but the defaults
241         // shouldn't require adding them. Fixing this means pulling Feature64Bit
242         // out of most of the target cpus in the .td file and making it set only
243         // as part of initialization via the TargetTriple.
244         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
245   }
246   return I.get();
247 }
248 
249 //===----------------------------------------------------------------------===//
250 // Pass Pipeline Configuration
251 //===----------------------------------------------------------------------===//
252 
253 namespace {
254 /// PPC Code Generator Pass Configuration Options.
255 class PPCPassConfig : public TargetPassConfig {
256 public:
257   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
258     : TargetPassConfig(TM, PM) {}
259 
260   PPCTargetMachine &getPPCTargetMachine() const {
261     return getTM<PPCTargetMachine>();
262   }
263 
264   void addIRPasses() override;
265   bool addPreISel() override;
266   bool addILPOpts() override;
267   bool addInstSelector() override;
268   void addMachineSSAOptimization() override;
269   void addPreRegAlloc() override;
270   void addPreSched2() override;
271   void addPreEmitPass() override;
272 };
273 } // namespace
274 
275 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
276   return new PPCPassConfig(this, PM);
277 }
278 
279 void PPCPassConfig::addIRPasses() {
280   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
281 
282   // For the BG/Q (or if explicitly requested), add explicit data prefetch
283   // intrinsics.
284   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
285                         getOptLevel() != CodeGenOpt::None;
286   if (EnablePrefetch.getNumOccurrences() > 0)
287     UsePrefetching = EnablePrefetch;
288   if (UsePrefetching)
289     addPass(createPPCLoopDataPrefetchPass());
290 
291   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
292     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
293     // and lower a GEP with multiple indices to either arithmetic operations or
294     // multiple GEPs with single index.
295     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
296     // Call EarlyCSE pass to find and remove subexpressions in the lowered
297     // result.
298     addPass(createEarlyCSEPass());
299     // Do loop invariant code motion in case part of the lowered result is
300     // invariant.
301     addPass(createLICMPass());
302   }
303 
304   TargetPassConfig::addIRPasses();
305 }
306 
307 bool PPCPassConfig::addPreISel() {
308   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
309     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
310 
311   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
312     addPass(createPPCCTRLoops(getPPCTargetMachine()));
313 
314   return false;
315 }
316 
317 bool PPCPassConfig::addILPOpts() {
318   addPass(&EarlyIfConverterID);
319   return true;
320 }
321 
322 bool PPCPassConfig::addInstSelector() {
323   // Install an instruction selector.
324   addPass(createPPCISelDag(getPPCTargetMachine()));
325 
326 #ifndef NDEBUG
327   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
328     addPass(createPPCCTRLoopsVerify());
329 #endif
330 
331   addPass(createPPCVSXCopyPass());
332   return false;
333 }
334 
335 void PPCPassConfig::addMachineSSAOptimization() {
336   TargetPassConfig::addMachineSSAOptimization();
337   // For little endian, remove where possible the vector swap instructions
338   // introduced at code generation to normalize vector element order.
339   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
340       !DisableVSXSwapRemoval)
341     addPass(createPPCVSXSwapRemovalPass());
342 }
343 
344 void PPCPassConfig::addPreRegAlloc() {
345   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
346   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
347              &PPCVSXFMAMutateID);
348   if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
349     addPass(createPPCTLSDynamicCallPass());
350   if (EnableExtraTOCRegDeps)
351     addPass(createPPCTOCRegDepsPass());
352 }
353 
354 void PPCPassConfig::addPreSched2() {
355   if (getOptLevel() != CodeGenOpt::None)
356     addPass(&IfConverterID);
357 }
358 
359 void PPCPassConfig::addPreEmitPass() {
360   if (getOptLevel() != CodeGenOpt::None)
361     addPass(createPPCEarlyReturnPass(), false);
362   // Must run branch selection immediately preceding the asm printer.
363   addPass(createPPCBranchSelectionPass(), false);
364 }
365 
366 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
367   return TargetIRAnalysis(
368       [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
369 }
370