1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCMacroFusion.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetObjectFile.h"
20 #include "PPCTargetTransformInfo.h"
21 #include "TargetInfo/PowerPCTargetInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Analysis/TargetTransformInfo.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
30 #include "llvm/CodeGen/GlobalISel/Localizer.h"
31 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
32 #include "llvm/CodeGen/MachineScheduler.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/MC/TargetRegistry.h"
40 #include "llvm/Pass.h"
41 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Transforms/Scalar.h"
46 #include <cassert>
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 
53 static cl::opt<bool>
54     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
55                            cl::desc("enable coalescing of duplicate branches for PPC"));
56 static cl::
57 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
58                         cl::desc("Disable CTR loops for PPC"));
59 
60 static cl::
61 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
62                             cl::desc("Disable PPC loop instr form prep"));
63 
64 static cl::opt<bool>
65 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
66   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
67 
68 static cl::
69 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
70                                 cl::desc("Disable VSX Swap Removal for PPC"));
71 
72 static cl::
73 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
74                             cl::desc("Disable machine peepholes for PPC"));
75 
76 static cl::opt<bool>
77 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
78              cl::desc("Enable optimizations on complex GEPs"),
79              cl::init(true));
80 
81 static cl::opt<bool>
82 EnablePrefetch("enable-ppc-prefetching",
83                   cl::desc("enable software prefetching on PPC"),
84                   cl::init(false), cl::Hidden);
85 
86 static cl::opt<bool>
87 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
88                       cl::desc("Add extra TOC register dependencies"),
89                       cl::init(true), cl::Hidden);
90 
91 static cl::opt<bool>
92 EnableMachineCombinerPass("ppc-machine-combiner",
93                           cl::desc("Enable the machine combiner pass"),
94                           cl::init(true), cl::Hidden);
95 
96 static cl::opt<bool>
97   ReduceCRLogical("ppc-reduce-cr-logicals",
98                   cl::desc("Expand eligible cr-logical binary ops to branches"),
99                   cl::init(true), cl::Hidden);
100 
101 static cl::opt<bool> EnablePPCGenScalarMASSEntries(
102     "enable-ppc-gen-scalar-mass", cl::init(false),
103     cl::desc("Enable lowering math functions to their corresponding MASS "
104              "(scalar) entries"),
105     cl::Hidden);
106 
107 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
108   // Register the targets
109   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
110   RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
111   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
112   RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
113 
114   PassRegistry &PR = *PassRegistry::getPassRegistry();
115 #ifndef NDEBUG
116   initializePPCCTRLoopsVerifyPass(PR);
117 #endif
118   initializePPCLoopInstrFormPrepPass(PR);
119   initializePPCTOCRegDepsPass(PR);
120   initializePPCEarlyReturnPass(PR);
121   initializePPCVSXCopyPass(PR);
122   initializePPCVSXFMAMutatePass(PR);
123   initializePPCVSXSwapRemovalPass(PR);
124   initializePPCReduceCRLogicalsPass(PR);
125   initializePPCBSelPass(PR);
126   initializePPCBranchCoalescingPass(PR);
127   initializePPCBoolRetToIntPass(PR);
128   initializePPCExpandISELPass(PR);
129   initializePPCPreEmitPeepholePass(PR);
130   initializePPCTLSDynamicCallPass(PR);
131   initializePPCMIPeepholePass(PR);
132   initializePPCLowerMASSVEntriesPass(PR);
133   initializePPCGenScalarMASSEntriesPass(PR);
134   initializePPCExpandAtomicPseudoPass(PR);
135   initializeGlobalISel(PR);
136 }
137 
138 static bool isLittleEndianTriple(const Triple &T) {
139   return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
140 }
141 
142 /// Return the datalayout string of a subtarget.
143 static std::string getDataLayoutString(const Triple &T) {
144   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
145   std::string Ret;
146 
147   // Most PPC* platforms are big endian, PPC(64)LE is little endian.
148   if (isLittleEndianTriple(T))
149     Ret = "e";
150   else
151     Ret = "E";
152 
153   Ret += DataLayout::getManglingComponent(T);
154 
155   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
156   // pointers.
157   if (!is64Bit || T.getOS() == Triple::Lv2)
158     Ret += "-p:32:32";
159 
160   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
161   // documentation are wrong; these are correct (i.e. "what gcc does").
162   Ret += "-i64:64";
163 
164   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
165   if (is64Bit)
166     Ret += "-n32:64";
167   else
168     Ret += "-n32";
169 
170   // Specify the vector alignment explicitly. For v256i1 and v512i1, the
171   // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
172   // which is 256 and 512 bytes - way over aligned.
173   if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
174     Ret += "-S128-v256:256:256-v512:512:512";
175 
176   return Ret;
177 }
178 
179 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
180                                       const Triple &TT) {
181   std::string FullFS = std::string(FS);
182 
183   // Make sure 64-bit features are available when CPUname is generic
184   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
185     if (!FullFS.empty())
186       FullFS = "+64bit," + FullFS;
187     else
188       FullFS = "+64bit";
189   }
190 
191   if (OL >= CodeGenOpt::Default) {
192     if (!FullFS.empty())
193       FullFS = "+crbits," + FullFS;
194     else
195       FullFS = "+crbits";
196   }
197 
198   if (OL != CodeGenOpt::None) {
199     if (!FullFS.empty())
200       FullFS = "+invariant-function-descriptors," + FullFS;
201     else
202       FullFS = "+invariant-function-descriptors";
203   }
204 
205   if (TT.isOSAIX()) {
206     if (!FullFS.empty())
207       FullFS = "+aix," + FullFS;
208     else
209       FullFS = "+aix";
210   }
211 
212   return FullFS;
213 }
214 
215 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
216   if (TT.isOSAIX())
217     return std::make_unique<TargetLoweringObjectFileXCOFF>();
218 
219   return std::make_unique<PPC64LinuxTargetObjectFile>();
220 }
221 
222 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
223                                                  const TargetOptions &Options) {
224   if (Options.MCOptions.getABIName().startswith("elfv1"))
225     return PPCTargetMachine::PPC_ABI_ELFv1;
226   else if (Options.MCOptions.getABIName().startswith("elfv2"))
227     return PPCTargetMachine::PPC_ABI_ELFv2;
228 
229   assert(Options.MCOptions.getABIName().empty() &&
230          "Unknown target-abi option!");
231 
232   if (TT.isMacOSX())
233     return PPCTargetMachine::PPC_ABI_UNKNOWN;
234 
235   switch (TT.getArch()) {
236   case Triple::ppc64le:
237     return PPCTargetMachine::PPC_ABI_ELFv2;
238   case Triple::ppc64:
239     return PPCTargetMachine::PPC_ABI_ELFv1;
240   default:
241     return PPCTargetMachine::PPC_ABI_UNKNOWN;
242   }
243 }
244 
245 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
246                                            Optional<Reloc::Model> RM) {
247   assert((!TT.isOSAIX() || !RM.hasValue() || *RM == Reloc::PIC_) &&
248          "Invalid relocation model for AIX.");
249 
250   if (RM.hasValue())
251     return *RM;
252 
253   // Big Endian PPC and AIX default to PIC.
254   if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
255     return Reloc::PIC_;
256 
257   // Rest are static by default.
258   return Reloc::Static;
259 }
260 
261 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
262                                                  Optional<CodeModel::Model> CM,
263                                                  bool JIT) {
264   if (CM) {
265     if (*CM == CodeModel::Tiny)
266       report_fatal_error("Target does not support the tiny CodeModel", false);
267     if (*CM == CodeModel::Kernel)
268       report_fatal_error("Target does not support the kernel CodeModel", false);
269     return *CM;
270   }
271 
272   if (JIT)
273     return CodeModel::Small;
274   if (TT.isOSAIX())
275     return CodeModel::Small;
276 
277   assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
278 
279   if (TT.isArch32Bit())
280     return CodeModel::Small;
281 
282   assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
283   return CodeModel::Medium;
284 }
285 
286 
287 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
288   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
289   ScheduleDAGMILive *DAG =
290     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
291                           std::make_unique<PPCPreRASchedStrategy>(C) :
292                           std::make_unique<GenericScheduler>(C));
293   // add DAG Mutations here.
294   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
295   if (ST.hasStoreFusion())
296     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
297   if (ST.hasFusion())
298     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
299 
300   return DAG;
301 }
302 
303 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
304   MachineSchedContext *C) {
305   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
306   ScheduleDAGMI *DAG =
307     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
308                       std::make_unique<PPCPostRASchedStrategy>(C) :
309                       std::make_unique<PostGenericScheduler>(C), true);
310   // add DAG Mutations here.
311   if (ST.hasStoreFusion())
312     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
313   if (ST.hasFusion())
314     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
315   return DAG;
316 }
317 
318 // The FeatureString here is a little subtle. We are modifying the feature
319 // string with what are (currently) non-function specific overrides as it goes
320 // into the LLVMTargetMachine constructor and then using the stored value in the
321 // Subtarget constructor below it.
322 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
323                                    StringRef CPU, StringRef FS,
324                                    const TargetOptions &Options,
325                                    Optional<Reloc::Model> RM,
326                                    Optional<CodeModel::Model> CM,
327                                    CodeGenOpt::Level OL, bool JIT)
328     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
329                         computeFSAdditions(FS, OL, TT), Options,
330                         getEffectiveRelocModel(TT, RM),
331                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
332       TLOF(createTLOF(getTargetTriple())),
333       TargetABI(computeTargetABI(TT, Options)),
334       Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
335   initAsmInfo();
336 }
337 
338 PPCTargetMachine::~PPCTargetMachine() = default;
339 
340 const PPCSubtarget *
341 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
342   Attribute CPUAttr = F.getFnAttribute("target-cpu");
343   Attribute FSAttr = F.getFnAttribute("target-features");
344 
345   std::string CPU =
346       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
347   std::string FS =
348       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
349 
350   // FIXME: This is related to the code below to reset the target options,
351   // we need to know whether or not the soft float flag is set on the
352   // function before we can generate a subtarget. We also need to use
353   // it as a key for the subtarget since that can be the only difference
354   // between two functions.
355   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
356   // If the soft float attribute is set on the function turn on the soft float
357   // subtarget feature.
358   if (SoftFloat)
359     FS += FS.empty() ? "-hard-float" : ",-hard-float";
360 
361   auto &I = SubtargetMap[CPU + FS];
362   if (!I) {
363     // This needs to be done before we create a new subtarget since any
364     // creation will depend on the TM and the code generation flags on the
365     // function that reside in TargetOptions.
366     resetTargetOptions(F);
367     I = std::make_unique<PPCSubtarget>(
368         TargetTriple, CPU,
369         // FIXME: It would be good to have the subtarget additions here
370         // not necessary. Anything that turns them on/off (overrides) ends
371         // up being put at the end of the feature string, but the defaults
372         // shouldn't require adding them. Fixing this means pulling Feature64Bit
373         // out of most of the target cpus in the .td file and making it set only
374         // as part of initialization via the TargetTriple.
375         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
376   }
377   return I.get();
378 }
379 
380 //===----------------------------------------------------------------------===//
381 // Pass Pipeline Configuration
382 //===----------------------------------------------------------------------===//
383 
384 namespace {
385 
386 /// PPC Code Generator Pass Configuration Options.
387 class PPCPassConfig : public TargetPassConfig {
388 public:
389   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
390     : TargetPassConfig(TM, PM) {
391     // At any optimization level above -O0 we use the Machine Scheduler and not
392     // the default Post RA List Scheduler.
393     if (TM.getOptLevel() != CodeGenOpt::None)
394       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
395   }
396 
397   PPCTargetMachine &getPPCTargetMachine() const {
398     return getTM<PPCTargetMachine>();
399   }
400 
401   void addIRPasses() override;
402   bool addPreISel() override;
403   bool addILPOpts() override;
404   bool addInstSelector() override;
405   void addMachineSSAOptimization() override;
406   void addPreRegAlloc() override;
407   void addPreSched2() override;
408   void addPreEmitPass() override;
409   void addPreEmitPass2() override;
410   // GlobalISEL
411   bool addIRTranslator() override;
412   bool addLegalizeMachineIR() override;
413   bool addRegBankSelect() override;
414   bool addGlobalInstructionSelect() override;
415 
416   ScheduleDAGInstrs *
417   createMachineScheduler(MachineSchedContext *C) const override {
418     return createPPCMachineScheduler(C);
419   }
420   ScheduleDAGInstrs *
421   createPostMachineScheduler(MachineSchedContext *C) const override {
422     return createPPCPostMachineScheduler(C);
423   }
424 };
425 
426 } // end anonymous namespace
427 
428 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
429   return new PPCPassConfig(*this, PM);
430 }
431 
432 void PPCPassConfig::addIRPasses() {
433   if (TM->getOptLevel() != CodeGenOpt::None)
434     addPass(createPPCBoolRetToIntPass());
435   addPass(createAtomicExpandPass());
436 
437   // Lower generic MASSV routines to PowerPC subtarget-specific entries.
438   addPass(createPPCLowerMASSVEntriesPass());
439 
440   // Generate PowerPC target-specific entries for scalar math functions
441   // that are available in IBM MASS (scalar) library.
442   if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
443       EnablePPCGenScalarMASSEntries) {
444     TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
445     addPass(createPPCGenScalarMASSEntriesPass());
446   }
447 
448   // If explicitly requested, add explicit data prefetch intrinsics.
449   if (EnablePrefetch.getNumOccurrences() > 0)
450     addPass(createLoopDataPrefetchPass());
451 
452   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
453     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
454     // and lower a GEP with multiple indices to either arithmetic operations or
455     // multiple GEPs with single index.
456     addPass(createSeparateConstOffsetFromGEPPass(true));
457     // Call EarlyCSE pass to find and remove subexpressions in the lowered
458     // result.
459     addPass(createEarlyCSEPass());
460     // Do loop invariant code motion in case part of the lowered result is
461     // invariant.
462     addPass(createLICMPass());
463   }
464 
465   TargetPassConfig::addIRPasses();
466 }
467 
468 bool PPCPassConfig::addPreISel() {
469   if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
470     addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
471 
472   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
473     addPass(createHardwareLoopsPass());
474 
475   return false;
476 }
477 
478 bool PPCPassConfig::addILPOpts() {
479   addPass(&EarlyIfConverterID);
480 
481   if (EnableMachineCombinerPass)
482     addPass(&MachineCombinerID);
483 
484   return true;
485 }
486 
487 bool PPCPassConfig::addInstSelector() {
488   // Install an instruction selector.
489   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
490 
491 #ifndef NDEBUG
492   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
493     addPass(createPPCCTRLoopsVerify());
494 #endif
495 
496   addPass(createPPCVSXCopyPass());
497   return false;
498 }
499 
500 void PPCPassConfig::addMachineSSAOptimization() {
501   // PPCBranchCoalescingPass need to be done before machine sinking
502   // since it merges empty blocks.
503   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
504     addPass(createPPCBranchCoalescingPass());
505   TargetPassConfig::addMachineSSAOptimization();
506   // For little endian, remove where possible the vector swap instructions
507   // introduced at code generation to normalize vector element order.
508   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
509       !DisableVSXSwapRemoval)
510     addPass(createPPCVSXSwapRemovalPass());
511   // Reduce the number of cr-logical ops.
512   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
513     addPass(createPPCReduceCRLogicalsPass());
514   // Target-specific peephole cleanups performed after instruction
515   // selection.
516   if (!DisableMIPeephole) {
517     addPass(createPPCMIPeepholePass());
518     addPass(&DeadMachineInstructionElimID);
519   }
520 }
521 
522 void PPCPassConfig::addPreRegAlloc() {
523   if (getOptLevel() != CodeGenOpt::None) {
524     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
525     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
526                &PPCVSXFMAMutateID);
527   }
528 
529   // FIXME: We probably don't need to run these for -fPIE.
530   if (getPPCTargetMachine().isPositionIndependent()) {
531     // FIXME: LiveVariables should not be necessary here!
532     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
533     // LiveVariables. This (unnecessary) dependency has been removed now,
534     // however a stage-2 clang build fails without LiveVariables computed here.
535     addPass(&LiveVariablesID);
536     addPass(createPPCTLSDynamicCallPass());
537   }
538   if (EnableExtraTOCRegDeps)
539     addPass(createPPCTOCRegDepsPass());
540 
541   if (getOptLevel() != CodeGenOpt::None)
542     addPass(&MachinePipelinerID);
543 }
544 
545 void PPCPassConfig::addPreSched2() {
546   if (getOptLevel() != CodeGenOpt::None)
547     addPass(&IfConverterID);
548 }
549 
550 void PPCPassConfig::addPreEmitPass() {
551   addPass(createPPCPreEmitPeepholePass());
552   addPass(createPPCExpandISELPass());
553 
554   if (getOptLevel() != CodeGenOpt::None)
555     addPass(createPPCEarlyReturnPass());
556 }
557 
558 void PPCPassConfig::addPreEmitPass2() {
559   // Schedule the expansion of AMOs at the last possible moment, avoiding the
560   // possibility for other passes to break the requirements for forward
561   // progress in the LL/SC block.
562   addPass(createPPCExpandAtomicPseudoPass());
563   // Must run branch selection immediately preceding the asm printer.
564   addPass(createPPCBranchSelectionPass());
565 }
566 
567 TargetTransformInfo
568 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
569   return TargetTransformInfo(PPCTTIImpl(this, F));
570 }
571 
572 bool PPCTargetMachine::isLittleEndian() const {
573   assert(Endianness != Endian::NOT_DETECTED &&
574          "Unable to determine endianness");
575   return Endianness == Endian::LITTLE;
576 }
577 
578 static MachineSchedRegistry
579 PPCPreRASchedRegistry("ppc-prera",
580                       "Run PowerPC PreRA specific scheduler",
581                       createPPCMachineScheduler);
582 
583 static MachineSchedRegistry
584 PPCPostRASchedRegistry("ppc-postra",
585                        "Run PowerPC PostRA specific scheduler",
586                        createPPCPostMachineScheduler);
587 
588 // Global ISEL
589 bool PPCPassConfig::addIRTranslator() {
590   addPass(new IRTranslator());
591   return false;
592 }
593 
594 bool PPCPassConfig::addLegalizeMachineIR() {
595   addPass(new Legalizer());
596   return false;
597 }
598 
599 bool PPCPassConfig::addRegBankSelect() {
600   addPass(new RegBankSelect());
601   return false;
602 }
603 
604 bool PPCPassConfig::addGlobalInstructionSelect() {
605   addPass(new InstructionSelect(getOptLevel()));
606   return false;
607 }
608