1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31                         cl::desc("Disable CTR loops for PPC"));
32 
33 static cl::
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35                             cl::desc("Disable PPC loop preinc prep"));
36 
37 static cl::opt<bool>
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
40 
41 static cl::opt<bool>
42 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
43              cl::desc("Enable optimizations on complex GEPs"),
44              cl::init(true));
45 
46 extern "C" void LLVMInitializePowerPCTarget() {
47   // Register the targets
48   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
49   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
50   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
51 }
52 
53 /// Return the datalayout string of a subtarget.
54 static std::string getDataLayoutString(const Triple &T) {
55   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
56   std::string Ret;
57 
58   // Most PPC* platforms are big endian, PPC64LE is little endian.
59   if (T.getArch() == Triple::ppc64le)
60     Ret = "e";
61   else
62     Ret = "E";
63 
64   Ret += DataLayout::getManglingComponent(T);
65 
66   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
67   // pointers.
68   if (!is64Bit || T.getOS() == Triple::Lv2)
69     Ret += "-p:32:32";
70 
71   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
72   // documentation are wrong; these are correct (i.e. "what gcc does").
73   if (is64Bit || !T.isOSDarwin())
74     Ret += "-i64:64";
75   else
76     Ret += "-f64:32:64";
77 
78   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
79   if (is64Bit)
80     Ret += "-n32:64";
81   else
82     Ret += "-n32";
83 
84   return Ret;
85 }
86 
87 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
88   std::string FullFS = FS;
89   Triple TargetTriple(TT);
90 
91   // Make sure 64-bit features are available when CPUname is generic
92   if (TargetTriple.getArch() == Triple::ppc64 ||
93       TargetTriple.getArch() == Triple::ppc64le) {
94     if (!FullFS.empty())
95       FullFS = "+64bit," + FullFS;
96     else
97       FullFS = "+64bit";
98   }
99 
100   if (OL >= CodeGenOpt::Default) {
101     if (!FullFS.empty())
102       FullFS = "+crbits," + FullFS;
103     else
104       FullFS = "+crbits";
105   }
106 
107   if (OL != CodeGenOpt::None) {
108      if (!FullFS.empty())
109       FullFS = "+invariant-function-descriptors," + FullFS;
110     else
111       FullFS = "+invariant-function-descriptors";
112   }
113 
114   return FullFS;
115 }
116 
117 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
118   // If it isn't a Mach-O file then it's going to be a linux ELF
119   // object file.
120   if (TT.isOSDarwin())
121     return make_unique<TargetLoweringObjectFileMachO>();
122 
123   return make_unique<PPC64LinuxTargetObjectFile>();
124 }
125 
126 // The FeatureString here is a little subtle. We are modifying the feature string
127 // with what are (currently) non-function specific overrides as it goes into the
128 // LLVMTargetMachine constructor and then using the stored value in the
129 // Subtarget constructor below it.
130 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
131                                    StringRef FS, const TargetOptions &Options,
132                                    Reloc::Model RM, CodeModel::Model CM,
133                                    CodeGenOpt::Level OL)
134     : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
135                         CM, OL),
136       TLOF(createTLOF(Triple(getTargetTriple()))),
137       DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
138   initAsmInfo();
139 }
140 
141 PPCTargetMachine::~PPCTargetMachine() {}
142 
143 void PPC32TargetMachine::anchor() { }
144 
145 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
146                                        StringRef CPU, StringRef FS,
147                                        const TargetOptions &Options,
148                                        Reloc::Model RM, CodeModel::Model CM,
149                                        CodeGenOpt::Level OL)
150   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
151 }
152 
153 void PPC64TargetMachine::anchor() { }
154 
155 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
156                                        StringRef CPU,  StringRef FS,
157                                        const TargetOptions &Options,
158                                        Reloc::Model RM, CodeModel::Model CM,
159                                        CodeGenOpt::Level OL)
160   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
161 }
162 
163 const PPCSubtarget *
164 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
165   AttributeSet FnAttrs = F.getAttributes();
166   Attribute CPUAttr =
167       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
168   Attribute FSAttr =
169       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
170 
171   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
172                         ? CPUAttr.getValueAsString().str()
173                         : TargetCPU;
174   std::string FS = !FSAttr.hasAttribute(Attribute::None)
175                        ? FSAttr.getValueAsString().str()
176                        : TargetFS;
177 
178   auto &I = SubtargetMap[CPU + FS];
179   if (!I) {
180     // This needs to be done before we create a new subtarget since any
181     // creation will depend on the TM and the code generation flags on the
182     // function that reside in TargetOptions.
183     resetTargetOptions(F);
184     I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
185   }
186   return I.get();
187 }
188 
189 //===----------------------------------------------------------------------===//
190 // Pass Pipeline Configuration
191 //===----------------------------------------------------------------------===//
192 
193 namespace {
194 /// PPC Code Generator Pass Configuration Options.
195 class PPCPassConfig : public TargetPassConfig {
196 public:
197   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
198     : TargetPassConfig(TM, PM) {}
199 
200   PPCTargetMachine &getPPCTargetMachine() const {
201     return getTM<PPCTargetMachine>();
202   }
203 
204   void addIRPasses() override;
205   bool addPreISel() override;
206   bool addILPOpts() override;
207   bool addInstSelector() override;
208   void addPreRegAlloc() override;
209   void addPreSched2() override;
210   void addPreEmitPass() override;
211 };
212 } // namespace
213 
214 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
215   return new PPCPassConfig(this, PM);
216 }
217 
218 void PPCPassConfig::addIRPasses() {
219   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
220 
221   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
222     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
223     // and lower a GEP with multiple indices to either arithmetic operations or
224     // multiple GEPs with single index.
225     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
226     // Call EarlyCSE pass to find and remove subexpressions in the lowered
227     // result.
228     addPass(createEarlyCSEPass());
229     // Do loop invariant code motion in case part of the lowered result is
230     // invariant.
231     addPass(createLICMPass());
232   }
233 
234   TargetPassConfig::addIRPasses();
235 }
236 
237 bool PPCPassConfig::addPreISel() {
238   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
239     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
240 
241   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
242     addPass(createPPCCTRLoops(getPPCTargetMachine()));
243 
244   return false;
245 }
246 
247 bool PPCPassConfig::addILPOpts() {
248   addPass(&EarlyIfConverterID);
249   return true;
250 }
251 
252 bool PPCPassConfig::addInstSelector() {
253   // Install an instruction selector.
254   addPass(createPPCISelDag(getPPCTargetMachine()));
255 
256 #ifndef NDEBUG
257   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
258     addPass(createPPCCTRLoopsVerify());
259 #endif
260 
261   addPass(createPPCVSXCopyPass());
262   return false;
263 }
264 
265 void PPCPassConfig::addPreRegAlloc() {
266   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
267   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
268              &PPCVSXFMAMutateID);
269 }
270 
271 void PPCPassConfig::addPreSched2() {
272   if (getOptLevel() != CodeGenOpt::None)
273     addPass(&IfConverterID);
274 }
275 
276 void PPCPassConfig::addPreEmitPass() {
277   if (getOptLevel() != CodeGenOpt::None)
278     addPass(createPPCEarlyReturnPass(), false);
279   // Must run branch selection immediately preceding the asm printer.
280   addPass(createPPCBranchSelectionPass(), false);
281 }
282 
283 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
284   return TargetIRAnalysis(
285       [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
286 }
287