1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31                         cl::desc("Disable CTR loops for PPC"));
32 
33 static cl::opt<bool>
34 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
35   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
36 
37 static cl::opt<bool>
38 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
39              cl::desc("Enable optimizations on complex GEPs"),
40              cl::init(true));
41 
42 extern "C" void LLVMInitializePowerPCTarget() {
43   // Register the targets
44   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
45   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
46   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
47 }
48 
49 /// Return the datalayout string of a subtarget.
50 static std::string getDataLayoutString(const Triple &T) {
51   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
52   std::string Ret;
53 
54   // Most PPC* platforms are big endian, PPC64LE is little endian.
55   if (T.getArch() == Triple::ppc64le)
56     Ret = "e";
57   else
58     Ret = "E";
59 
60   Ret += DataLayout::getManglingComponent(T);
61 
62   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
63   // pointers.
64   if (!is64Bit || T.getOS() == Triple::Lv2)
65     Ret += "-p:32:32";
66 
67   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
68   // documentation are wrong; these are correct (i.e. "what gcc does").
69   if (is64Bit || !T.isOSDarwin())
70     Ret += "-i64:64";
71   else
72     Ret += "-f64:32:64";
73 
74   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
75   if (is64Bit)
76     Ret += "-n32:64";
77   else
78     Ret += "-n32";
79 
80   return Ret;
81 }
82 
83 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
84   std::string FullFS = FS;
85   Triple TargetTriple(TT);
86 
87   // Make sure 64-bit features are available when CPUname is generic
88   if (TargetTriple.getArch() == Triple::ppc64 ||
89       TargetTriple.getArch() == Triple::ppc64le) {
90     if (!FullFS.empty())
91       FullFS = "+64bit," + FullFS;
92     else
93       FullFS = "+64bit";
94   }
95 
96   if (OL >= CodeGenOpt::Default) {
97     if (!FullFS.empty())
98       FullFS = "+crbits," + FullFS;
99     else
100       FullFS = "+crbits";
101   }
102 
103   if (OL != CodeGenOpt::None) {
104      if (!FullFS.empty())
105       FullFS = "+invariant-function-descriptors," + FullFS;
106     else
107       FullFS = "+invariant-function-descriptors";
108   }
109 
110   return FullFS;
111 }
112 
113 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
114   // If it isn't a Mach-O file then it's going to be a linux ELF
115   // object file.
116   if (TT.isOSDarwin())
117     return make_unique<TargetLoweringObjectFileMachO>();
118 
119   return make_unique<PPC64LinuxTargetObjectFile>();
120 }
121 
122 // The FeatureString here is a little subtle. We are modifying the feature string
123 // with what are (currently) non-function specific overrides as it goes into the
124 // LLVMTargetMachine constructor and then using the stored value in the
125 // Subtarget constructor below it.
126 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
127                                    StringRef FS, const TargetOptions &Options,
128                                    Reloc::Model RM, CodeModel::Model CM,
129                                    CodeGenOpt::Level OL)
130     : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
131                         CM, OL),
132       TLOF(createTLOF(Triple(getTargetTriple()))),
133       DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
134   initAsmInfo();
135 }
136 
137 PPCTargetMachine::~PPCTargetMachine() {}
138 
139 void PPC32TargetMachine::anchor() { }
140 
141 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
142                                        StringRef CPU, StringRef FS,
143                                        const TargetOptions &Options,
144                                        Reloc::Model RM, CodeModel::Model CM,
145                                        CodeGenOpt::Level OL)
146   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
147 }
148 
149 void PPC64TargetMachine::anchor() { }
150 
151 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
152                                        StringRef CPU,  StringRef FS,
153                                        const TargetOptions &Options,
154                                        Reloc::Model RM, CodeModel::Model CM,
155                                        CodeGenOpt::Level OL)
156   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
157 }
158 
159 const PPCSubtarget *
160 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
161   AttributeSet FnAttrs = F.getAttributes();
162   Attribute CPUAttr =
163       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
164   Attribute FSAttr =
165       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
166 
167   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
168                         ? CPUAttr.getValueAsString().str()
169                         : TargetCPU;
170   std::string FS = !FSAttr.hasAttribute(Attribute::None)
171                        ? FSAttr.getValueAsString().str()
172                        : TargetFS;
173 
174   auto &I = SubtargetMap[CPU + FS];
175   if (!I) {
176     // This needs to be done before we create a new subtarget since any
177     // creation will depend on the TM and the code generation flags on the
178     // function that reside in TargetOptions.
179     resetTargetOptions(F);
180     I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
181   }
182   return I.get();
183 }
184 
185 //===----------------------------------------------------------------------===//
186 // Pass Pipeline Configuration
187 //===----------------------------------------------------------------------===//
188 
189 namespace {
190 /// PPC Code Generator Pass Configuration Options.
191 class PPCPassConfig : public TargetPassConfig {
192 public:
193   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
194     : TargetPassConfig(TM, PM) {}
195 
196   PPCTargetMachine &getPPCTargetMachine() const {
197     return getTM<PPCTargetMachine>();
198   }
199 
200   void addIRPasses() override;
201   bool addPreISel() override;
202   bool addILPOpts() override;
203   bool addInstSelector() override;
204   void addPreRegAlloc() override;
205   void addPreSched2() override;
206   void addPreEmitPass() override;
207 };
208 } // namespace
209 
210 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
211   return new PPCPassConfig(this, PM);
212 }
213 
214 void PPCPassConfig::addIRPasses() {
215   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
216 
217   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
218     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
219     // and lower a GEP with multiple indices to either arithmetic operations or
220     // multiple GEPs with single index.
221     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
222     // Call EarlyCSE pass to find and remove subexpressions in the lowered
223     // result.
224     addPass(createEarlyCSEPass());
225     // Do loop invariant code motion in case part of the lowered result is
226     // invariant.
227     addPass(createLICMPass());
228   }
229 
230   TargetPassConfig::addIRPasses();
231 }
232 
233 bool PPCPassConfig::addPreISel() {
234   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
235     addPass(createPPCCTRLoops(getPPCTargetMachine()));
236 
237   return false;
238 }
239 
240 bool PPCPassConfig::addILPOpts() {
241   addPass(&EarlyIfConverterID);
242   return true;
243 }
244 
245 bool PPCPassConfig::addInstSelector() {
246   // Install an instruction selector.
247   addPass(createPPCISelDag(getPPCTargetMachine()));
248 
249 #ifndef NDEBUG
250   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
251     addPass(createPPCCTRLoopsVerify());
252 #endif
253 
254   addPass(createPPCVSXCopyPass());
255   return false;
256 }
257 
258 void PPCPassConfig::addPreRegAlloc() {
259   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
260   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
261              &PPCVSXFMAMutateID);
262 }
263 
264 void PPCPassConfig::addPreSched2() {
265   if (getOptLevel() != CodeGenOpt::None)
266     addPass(&IfConverterID);
267 }
268 
269 void PPCPassConfig::addPreEmitPass() {
270   if (getOptLevel() != CodeGenOpt::None)
271     addPass(createPPCEarlyReturnPass(), false);
272   // Must run branch selection immediately preceding the asm printer.
273   addPass(createPPCBranchSelectionPass(), false);
274 }
275 
276 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
277   return TargetIRAnalysis(
278       [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
279 }
280