1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 static cl::
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                         cl::desc("Disable CTR loops for PPC"));
28 
29 extern "C" void LLVMInitializePowerPCTarget() {
30   // Register the targets
31   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
34 }
35 
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38   const Triple &T = ST.getTargetTriple();
39 
40   // PPC is big endian.
41   std::string Ret = "E";
42 
43   Ret += DataLayout::getManglingComponent(T);
44 
45   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
46   // pointers.
47   if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
48     Ret += "-p:32:32";
49 
50   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
51   // documentation are wrong; these are correct (i.e. "what gcc does").
52   if (ST.isPPC64() || ST.isSVR4ABI())
53     Ret += "-i64:64";
54   else
55     Ret += "-f64:32:64";
56 
57   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
58   if (ST.isPPC64())
59     Ret += "-n32:64";
60   else
61     Ret += "-n32";
62 
63   return Ret;
64 }
65 
66 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
67                                    StringRef CPU, StringRef FS,
68                                    const TargetOptions &Options,
69                                    Reloc::Model RM, CodeModel::Model CM,
70                                    CodeGenOpt::Level OL,
71                                    bool is64Bit)
72   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73     Subtarget(TT, CPU, FS, is64Bit),
74     DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
75     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
76     TLInfo(*this), TSInfo(*this),
77     InstrItins(Subtarget.getInstrItineraryData()) {
78 
79   // The binutils for the BG/P are too old for CFI.
80   if (Subtarget.isBGP())
81     setMCUseCFI(false);
82   initAsmInfo();
83 }
84 
85 void PPC32TargetMachine::anchor() { }
86 
87 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
88                                        StringRef CPU, StringRef FS,
89                                        const TargetOptions &Options,
90                                        Reloc::Model RM, CodeModel::Model CM,
91                                        CodeGenOpt::Level OL)
92   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
93 }
94 
95 void PPC64TargetMachine::anchor() { }
96 
97 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
98                                        StringRef CPU,  StringRef FS,
99                                        const TargetOptions &Options,
100                                        Reloc::Model RM, CodeModel::Model CM,
101                                        CodeGenOpt::Level OL)
102   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
103 }
104 
105 
106 //===----------------------------------------------------------------------===//
107 // Pass Pipeline Configuration
108 //===----------------------------------------------------------------------===//
109 
110 namespace {
111 /// PPC Code Generator Pass Configuration Options.
112 class PPCPassConfig : public TargetPassConfig {
113 public:
114   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
115     : TargetPassConfig(TM, PM) {}
116 
117   PPCTargetMachine &getPPCTargetMachine() const {
118     return getTM<PPCTargetMachine>();
119   }
120 
121   const PPCSubtarget &getPPCSubtarget() const {
122     return *getPPCTargetMachine().getSubtargetImpl();
123   }
124 
125   virtual bool addPreISel();
126   virtual bool addILPOpts();
127   virtual bool addInstSelector();
128   virtual bool addPreSched2();
129   virtual bool addPreEmitPass();
130 };
131 } // namespace
132 
133 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
134   return new PPCPassConfig(this, PM);
135 }
136 
137 bool PPCPassConfig::addPreISel() {
138   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
139     addPass(createPPCCTRLoops(getPPCTargetMachine()));
140 
141   return false;
142 }
143 
144 bool PPCPassConfig::addILPOpts() {
145   if (getPPCSubtarget().hasISEL()) {
146     addPass(&EarlyIfConverterID);
147     return true;
148   }
149 
150   return false;
151 }
152 
153 bool PPCPassConfig::addInstSelector() {
154   // Install an instruction selector.
155   addPass(createPPCISelDag(getPPCTargetMachine()));
156 
157 #ifndef NDEBUG
158   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
159     addPass(createPPCCTRLoopsVerify());
160 #endif
161 
162   return false;
163 }
164 
165 bool PPCPassConfig::addPreSched2() {
166   if (getOptLevel() != CodeGenOpt::None)
167     addPass(&IfConverterID);
168 
169   return true;
170 }
171 
172 bool PPCPassConfig::addPreEmitPass() {
173   if (getOptLevel() != CodeGenOpt::None)
174     addPass(createPPCEarlyReturnPass());
175   // Must run branch selection immediately preceding the asm printer.
176   addPass(createPPCBranchSelectionPass());
177   return false;
178 }
179 
180 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
181                                       JITCodeEmitter &JCE) {
182   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
183   // writing?
184   Subtarget.SetJITMode();
185 
186   // Machine code emitter pass for PowerPC.
187   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
188 
189   return false;
190 }
191 
192 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
193   // Add first the target-independent BasicTTI pass, then our PPC pass. This
194   // allows the PPC pass to delegate to the target independent layer when
195   // appropriate.
196   PM.add(createBasicTargetTransformInfoPass(this));
197   PM.add(createPPCTargetTransformInfoPass(this));
198 }
199 
200