1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/CodeGen/MachineScheduler.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CodeGen.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include <cassert>
39 #include <memory>
40 #include <string>
41 
42 using namespace llvm;
43 
44 
45 static cl::opt<bool>
46     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
47                            cl::desc("enable coalescing of duplicate branches for PPC"));
48 static cl::
49 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
50                         cl::desc("Disable CTR loops for PPC"));
51 
52 static cl::
53 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
54                             cl::desc("Disable PPC loop preinc prep"));
55 
56 static cl::opt<bool>
57 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
58   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
59 
60 static cl::
61 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
62                                 cl::desc("Disable VSX Swap Removal for PPC"));
63 
64 static cl::
65 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
66                               cl::desc("Disable QPX load splat simplification"));
67 
68 static cl::
69 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
70                             cl::desc("Disable machine peepholes for PPC"));
71 
72 static cl::opt<bool>
73 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
74              cl::desc("Enable optimizations on complex GEPs"),
75              cl::init(true));
76 
77 static cl::opt<bool>
78 EnablePrefetch("enable-ppc-prefetching",
79                   cl::desc("disable software prefetching on PPC"),
80                   cl::init(false), cl::Hidden);
81 
82 static cl::opt<bool>
83 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
84                       cl::desc("Add extra TOC register dependencies"),
85                       cl::init(true), cl::Hidden);
86 
87 static cl::opt<bool>
88 EnableMachineCombinerPass("ppc-machine-combiner",
89                           cl::desc("Enable the machine combiner pass"),
90                           cl::init(true), cl::Hidden);
91 
92 static cl::opt<bool>
93   ReduceCRLogical("ppc-reduce-cr-logicals",
94                   cl::desc("Expand eligible cr-logical binary ops to branches"),
95                   cl::init(false), cl::Hidden);
96 extern "C" void LLVMInitializePowerPCTarget() {
97   // Register the targets
98   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
99   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
100   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
101 
102   PassRegistry &PR = *PassRegistry::getPassRegistry();
103   initializePPCCTRLoopsPass(PR);
104 #ifndef NDEBUG
105   initializePPCCTRLoopsVerifyPass(PR);
106 #endif
107   initializePPCLoopPreIncPrepPass(PR);
108   initializePPCTOCRegDepsPass(PR);
109   initializePPCEarlyReturnPass(PR);
110   initializePPCVSXCopyPass(PR);
111   initializePPCVSXFMAMutatePass(PR);
112   initializePPCVSXSwapRemovalPass(PR);
113   initializePPCReduceCRLogicalsPass(PR);
114   initializePPCBSelPass(PR);
115   initializePPCBranchCoalescingPass(PR);
116   initializePPCQPXLoadSplatPass(PR);
117   initializePPCBoolRetToIntPass(PR);
118   initializePPCExpandISELPass(PR);
119   initializePPCPreEmitPeepholePass(PR);
120   initializePPCTLSDynamicCallPass(PR);
121   initializePPCMIPeepholePass(PR);
122 }
123 
124 /// Return the datalayout string of a subtarget.
125 static std::string getDataLayoutString(const Triple &T) {
126   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
127   std::string Ret;
128 
129   // Most PPC* platforms are big endian, PPC64LE is little endian.
130   if (T.getArch() == Triple::ppc64le)
131     Ret = "e";
132   else
133     Ret = "E";
134 
135   Ret += DataLayout::getManglingComponent(T);
136 
137   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
138   // pointers.
139   if (!is64Bit || T.getOS() == Triple::Lv2)
140     Ret += "-p:32:32";
141 
142   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
143   // documentation are wrong; these are correct (i.e. "what gcc does").
144   if (is64Bit || !T.isOSDarwin())
145     Ret += "-i64:64";
146   else
147     Ret += "-f64:32:64";
148 
149   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
150   if (is64Bit)
151     Ret += "-n32:64";
152   else
153     Ret += "-n32";
154 
155   return Ret;
156 }
157 
158 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
159                                       const Triple &TT) {
160   std::string FullFS = FS;
161 
162   // Make sure 64-bit features are available when CPUname is generic
163   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
164     if (!FullFS.empty())
165       FullFS = "+64bit," + FullFS;
166     else
167       FullFS = "+64bit";
168   }
169 
170   if (OL >= CodeGenOpt::Default) {
171     if (!FullFS.empty())
172       FullFS = "+crbits," + FullFS;
173     else
174       FullFS = "+crbits";
175   }
176 
177   if (OL != CodeGenOpt::None) {
178     if (!FullFS.empty())
179       FullFS = "+invariant-function-descriptors," + FullFS;
180     else
181       FullFS = "+invariant-function-descriptors";
182   }
183 
184   return FullFS;
185 }
186 
187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
188   // If it isn't a Mach-O file then it's going to be a linux ELF
189   // object file.
190   if (TT.isOSDarwin())
191     return llvm::make_unique<TargetLoweringObjectFileMachO>();
192 
193   return llvm::make_unique<PPC64LinuxTargetObjectFile>();
194 }
195 
196 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
197                                                  const TargetOptions &Options) {
198   if (TT.isOSDarwin())
199     report_fatal_error("Darwin is no longer supported for PowerPC");
200 
201   if (Options.MCOptions.getABIName().startswith("elfv1"))
202     return PPCTargetMachine::PPC_ABI_ELFv1;
203   else if (Options.MCOptions.getABIName().startswith("elfv2"))
204     return PPCTargetMachine::PPC_ABI_ELFv2;
205 
206   assert(Options.MCOptions.getABIName().empty() &&
207          "Unknown target-abi option!");
208 
209   if (TT.isMacOSX())
210     return PPCTargetMachine::PPC_ABI_UNKNOWN;
211 
212   switch (TT.getArch()) {
213   case Triple::ppc64le:
214     return PPCTargetMachine::PPC_ABI_ELFv2;
215   case Triple::ppc64:
216     return PPCTargetMachine::PPC_ABI_ELFv1;
217   default:
218     return PPCTargetMachine::PPC_ABI_UNKNOWN;
219   }
220 }
221 
222 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
223                                            Optional<Reloc::Model> RM) {
224   if (RM.hasValue())
225     return *RM;
226 
227   // Darwin defaults to dynamic-no-pic.
228   if (TT.isOSDarwin())
229     return Reloc::DynamicNoPIC;
230 
231   // Big Endian PPC is PIC by default.
232   if (TT.getArch() == Triple::ppc64)
233     return Reloc::PIC_;
234 
235   // Rest are static by default.
236   return Reloc::Static;
237 }
238 
239 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
240                                                  Optional<CodeModel::Model> CM,
241                                                  bool JIT) {
242   if (CM) {
243     if (*CM == CodeModel::Tiny)
244       report_fatal_error("Target does not support the tiny CodeModel");
245     if (*CM == CodeModel::Kernel)
246       report_fatal_error("Target does not support the kernel CodeModel");
247     return *CM;
248   }
249   if (!TT.isOSDarwin() && !JIT &&
250       (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
251     return CodeModel::Medium;
252   return CodeModel::Small;
253 }
254 
255 
256 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
257   ScheduleDAGMILive *DAG =
258     new ScheduleDAGMILive(C, llvm::make_unique<PPCPreRASchedStrategy>(C));
259   // add DAG Mutations here.
260   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
261   return DAG;
262 }
263 
264 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
265   MachineSchedContext *C) {
266   ScheduleDAGMI *DAG =
267     new ScheduleDAGMI(C, llvm::make_unique<PPCPostRASchedStrategy>(C), true);
268   // add DAG Mutations here.
269   return DAG;
270 }
271 
272 // The FeatureString here is a little subtle. We are modifying the feature
273 // string with what are (currently) non-function specific overrides as it goes
274 // into the LLVMTargetMachine constructor and then using the stored value in the
275 // Subtarget constructor below it.
276 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
277                                    StringRef CPU, StringRef FS,
278                                    const TargetOptions &Options,
279                                    Optional<Reloc::Model> RM,
280                                    Optional<CodeModel::Model> CM,
281                                    CodeGenOpt::Level OL, bool JIT)
282     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
283                         computeFSAdditions(FS, OL, TT), Options,
284                         getEffectiveRelocModel(TT, RM),
285                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
286       TLOF(createTLOF(getTargetTriple())),
287       TargetABI(computeTargetABI(TT, Options)) {
288   initAsmInfo();
289 }
290 
291 PPCTargetMachine::~PPCTargetMachine() = default;
292 
293 const PPCSubtarget *
294 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
295   Attribute CPUAttr = F.getFnAttribute("target-cpu");
296   Attribute FSAttr = F.getFnAttribute("target-features");
297 
298   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
299                         ? CPUAttr.getValueAsString().str()
300                         : TargetCPU;
301   std::string FS = !FSAttr.hasAttribute(Attribute::None)
302                        ? FSAttr.getValueAsString().str()
303                        : TargetFS;
304 
305   // FIXME: This is related to the code below to reset the target options,
306   // we need to know whether or not the soft float flag is set on the
307   // function before we can generate a subtarget. We also need to use
308   // it as a key for the subtarget since that can be the only difference
309   // between two functions.
310   bool SoftFloat =
311       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
312   // If the soft float attribute is set on the function turn on the soft float
313   // subtarget feature.
314   if (SoftFloat)
315     FS += FS.empty() ? "-hard-float" : ",-hard-float";
316 
317   auto &I = SubtargetMap[CPU + FS];
318   if (!I) {
319     // This needs to be done before we create a new subtarget since any
320     // creation will depend on the TM and the code generation flags on the
321     // function that reside in TargetOptions.
322     resetTargetOptions(F);
323     I = llvm::make_unique<PPCSubtarget>(
324         TargetTriple, CPU,
325         // FIXME: It would be good to have the subtarget additions here
326         // not necessary. Anything that turns them on/off (overrides) ends
327         // up being put at the end of the feature string, but the defaults
328         // shouldn't require adding them. Fixing this means pulling Feature64Bit
329         // out of most of the target cpus in the .td file and making it set only
330         // as part of initialization via the TargetTriple.
331         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
332   }
333   return I.get();
334 }
335 
336 //===----------------------------------------------------------------------===//
337 // Pass Pipeline Configuration
338 //===----------------------------------------------------------------------===//
339 
340 namespace {
341 
342 /// PPC Code Generator Pass Configuration Options.
343 class PPCPassConfig : public TargetPassConfig {
344 public:
345   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
346     : TargetPassConfig(TM, PM) {
347     // At any optimization level above -O0 we use the Machine Scheduler and not
348     // the default Post RA List Scheduler.
349     if (TM.getOptLevel() != CodeGenOpt::None)
350       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
351   }
352 
353   PPCTargetMachine &getPPCTargetMachine() const {
354     return getTM<PPCTargetMachine>();
355   }
356 
357   void addIRPasses() override;
358   bool addPreISel() override;
359   bool addILPOpts() override;
360   bool addInstSelector() override;
361   void addMachineSSAOptimization() override;
362   void addPreRegAlloc() override;
363   void addPreSched2() override;
364   void addPreEmitPass() override;
365   ScheduleDAGInstrs *
366   createMachineScheduler(MachineSchedContext *C) const override {
367     const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
368     if (ST.usePPCPreRASchedStrategy())
369       return createPPCMachineScheduler(C);
370     return nullptr;
371   }
372   ScheduleDAGInstrs *
373   createPostMachineScheduler(MachineSchedContext *C) const override {
374     const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
375     if (ST.usePPCPostRASchedStrategy())
376       return createPPCPostMachineScheduler(C);
377     return nullptr;
378   }
379 };
380 
381 } // end anonymous namespace
382 
383 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
384   return new PPCPassConfig(*this, PM);
385 }
386 
387 void PPCPassConfig::addIRPasses() {
388   if (TM->getOptLevel() != CodeGenOpt::None)
389     addPass(createPPCBoolRetToIntPass());
390   addPass(createAtomicExpandPass());
391 
392   // For the BG/Q (or if explicitly requested), add explicit data prefetch
393   // intrinsics.
394   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
395                         getOptLevel() != CodeGenOpt::None;
396   if (EnablePrefetch.getNumOccurrences() > 0)
397     UsePrefetching = EnablePrefetch;
398   if (UsePrefetching)
399     addPass(createLoopDataPrefetchPass());
400 
401   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
402     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
403     // and lower a GEP with multiple indices to either arithmetic operations or
404     // multiple GEPs with single index.
405     addPass(createSeparateConstOffsetFromGEPPass(true));
406     // Call EarlyCSE pass to find and remove subexpressions in the lowered
407     // result.
408     addPass(createEarlyCSEPass());
409     // Do loop invariant code motion in case part of the lowered result is
410     // invariant.
411     addPass(createLICMPass());
412   }
413 
414   TargetPassConfig::addIRPasses();
415 }
416 
417 bool PPCPassConfig::addPreISel() {
418   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
419     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
420 
421   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
422     addPass(createPPCCTRLoops());
423 
424   return false;
425 }
426 
427 bool PPCPassConfig::addILPOpts() {
428   addPass(&EarlyIfConverterID);
429 
430   if (EnableMachineCombinerPass)
431     addPass(&MachineCombinerID);
432 
433   return true;
434 }
435 
436 bool PPCPassConfig::addInstSelector() {
437   // Install an instruction selector.
438   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
439 
440 #ifndef NDEBUG
441   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
442     addPass(createPPCCTRLoopsVerify());
443 #endif
444 
445   addPass(createPPCVSXCopyPass());
446   return false;
447 }
448 
449 void PPCPassConfig::addMachineSSAOptimization() {
450   // PPCBranchCoalescingPass need to be done before machine sinking
451   // since it merges empty blocks.
452   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
453     addPass(createPPCBranchCoalescingPass());
454   TargetPassConfig::addMachineSSAOptimization();
455   // For little endian, remove where possible the vector swap instructions
456   // introduced at code generation to normalize vector element order.
457   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
458       !DisableVSXSwapRemoval)
459     addPass(createPPCVSXSwapRemovalPass());
460   // Reduce the number of cr-logical ops.
461   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
462     addPass(createPPCReduceCRLogicalsPass());
463   // Target-specific peephole cleanups performed after instruction
464   // selection.
465   if (!DisableMIPeephole) {
466     addPass(createPPCMIPeepholePass());
467     addPass(&DeadMachineInstructionElimID);
468   }
469 }
470 
471 void PPCPassConfig::addPreRegAlloc() {
472   if (getOptLevel() != CodeGenOpt::None) {
473     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
474     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
475                &PPCVSXFMAMutateID);
476   }
477 
478   // FIXME: We probably don't need to run these for -fPIE.
479   if (getPPCTargetMachine().isPositionIndependent()) {
480     // FIXME: LiveVariables should not be necessary here!
481     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
482     // LiveVariables. This (unnecessary) dependency has been removed now,
483     // however a stage-2 clang build fails without LiveVariables computed here.
484     addPass(&LiveVariablesID, false);
485     addPass(createPPCTLSDynamicCallPass());
486   }
487   if (EnableExtraTOCRegDeps)
488     addPass(createPPCTOCRegDepsPass());
489 }
490 
491 void PPCPassConfig::addPreSched2() {
492   if (getOptLevel() != CodeGenOpt::None) {
493     addPass(&IfConverterID);
494 
495     // This optimization must happen after anything that might do store-to-load
496     // forwarding. Here we're after RA (and, thus, when spills are inserted)
497     // but before post-RA scheduling.
498     if (!DisableQPXLoadSplat)
499       addPass(createPPCQPXLoadSplatPass());
500   }
501 }
502 
503 void PPCPassConfig::addPreEmitPass() {
504   addPass(createPPCPreEmitPeepholePass());
505   addPass(createPPCExpandISELPass());
506 
507   if (getOptLevel() != CodeGenOpt::None)
508     addPass(createPPCEarlyReturnPass(), false);
509   // Must run branch selection immediately preceding the asm printer.
510   addPass(createPPCBranchSelectionPass(), false);
511 }
512 
513 TargetTransformInfo
514 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
515   return TargetTransformInfo(PPCTTIImpl(this, F));
516 }
517 
518 static MachineSchedRegistry
519 PPCPreRASchedRegistry("ppc-prera",
520                       "Run PowerPC PreRA specific scheduler",
521                       createPPCMachineScheduler);
522 
523 static MachineSchedRegistry
524 PPCPostRASchedRegistry("ppc-postra",
525                        "Run PowerPC PostRA specific scheduler",
526                        createPPCPostMachineScheduler);
527