1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "TargetInfo/PowerPCTargetInfo.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Pass.h"
33 #include "llvm/Support/CodeGen.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Transforms/Scalar.h"
39 #include <cassert>
40 #include <memory>
41 #include <string>
42 
43 using namespace llvm;
44 
45 
46 static cl::opt<bool>
47     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
48                            cl::desc("enable coalescing of duplicate branches for PPC"));
49 static cl::
50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
51                         cl::desc("Disable CTR loops for PPC"));
52 
53 static cl::
54 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
55                             cl::desc("Disable PPC loop preinc prep"));
56 
57 static cl::opt<bool>
58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
59   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
60 
61 static cl::
62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
63                                 cl::desc("Disable VSX Swap Removal for PPC"));
64 
65 static cl::
66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
67                               cl::desc("Disable QPX load splat simplification"));
68 
69 static cl::
70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
71                             cl::desc("Disable machine peepholes for PPC"));
72 
73 static cl::opt<bool>
74 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
75              cl::desc("Enable optimizations on complex GEPs"),
76              cl::init(true));
77 
78 static cl::opt<bool>
79 EnablePrefetch("enable-ppc-prefetching",
80                   cl::desc("disable software prefetching on PPC"),
81                   cl::init(false), cl::Hidden);
82 
83 static cl::opt<bool>
84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
85                       cl::desc("Add extra TOC register dependencies"),
86                       cl::init(true), cl::Hidden);
87 
88 static cl::opt<bool>
89 EnableMachineCombinerPass("ppc-machine-combiner",
90                           cl::desc("Enable the machine combiner pass"),
91                           cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool>
94   ReduceCRLogical("ppc-reduce-cr-logicals",
95                   cl::desc("Expand eligible cr-logical binary ops to branches"),
96                   cl::init(true), cl::Hidden);
97 extern "C" void LLVMInitializePowerPCTarget() {
98   // Register the targets
99   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
100   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
101   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
102 
103   PassRegistry &PR = *PassRegistry::getPassRegistry();
104 #ifndef NDEBUG
105   initializePPCCTRLoopsVerifyPass(PR);
106 #endif
107   initializePPCLoopPreIncPrepPass(PR);
108   initializePPCTOCRegDepsPass(PR);
109   initializePPCEarlyReturnPass(PR);
110   initializePPCVSXCopyPass(PR);
111   initializePPCVSXFMAMutatePass(PR);
112   initializePPCVSXSwapRemovalPass(PR);
113   initializePPCReduceCRLogicalsPass(PR);
114   initializePPCBSelPass(PR);
115   initializePPCBranchCoalescingPass(PR);
116   initializePPCQPXLoadSplatPass(PR);
117   initializePPCBoolRetToIntPass(PR);
118   initializePPCExpandISELPass(PR);
119   initializePPCPreEmitPeepholePass(PR);
120   initializePPCTLSDynamicCallPass(PR);
121   initializePPCMIPeepholePass(PR);
122 }
123 
124 /// Return the datalayout string of a subtarget.
125 static std::string getDataLayoutString(const Triple &T) {
126   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
127   std::string Ret;
128 
129   // Most PPC* platforms are big endian, PPC64LE is little endian.
130   if (T.getArch() == Triple::ppc64le)
131     Ret = "e";
132   else
133     Ret = "E";
134 
135   Ret += DataLayout::getManglingComponent(T);
136 
137   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
138   // pointers.
139   if (!is64Bit || T.getOS() == Triple::Lv2)
140     Ret += "-p:32:32";
141 
142   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
143   // documentation are wrong; these are correct (i.e. "what gcc does").
144   if (is64Bit || !T.isOSDarwin())
145     Ret += "-i64:64";
146   else
147     Ret += "-f64:32:64";
148 
149   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
150   if (is64Bit)
151     Ret += "-n32:64";
152   else
153     Ret += "-n32";
154 
155   return Ret;
156 }
157 
158 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
159                                       const Triple &TT) {
160   std::string FullFS = FS;
161 
162   // Make sure 64-bit features are available when CPUname is generic
163   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
164     if (!FullFS.empty())
165       FullFS = "+64bit," + FullFS;
166     else
167       FullFS = "+64bit";
168   }
169 
170   if (OL >= CodeGenOpt::Default) {
171     if (!FullFS.empty())
172       FullFS = "+crbits," + FullFS;
173     else
174       FullFS = "+crbits";
175   }
176 
177   if (OL != CodeGenOpt::None) {
178     if (!FullFS.empty())
179       FullFS = "+invariant-function-descriptors," + FullFS;
180     else
181       FullFS = "+invariant-function-descriptors";
182   }
183 
184   return FullFS;
185 }
186 
187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
188   if (TT.isOSDarwin())
189     return std::make_unique<TargetLoweringObjectFileMachO>();
190 
191   if (TT.isOSAIX())
192     return std::make_unique<TargetLoweringObjectFileXCOFF>();
193 
194   return std::make_unique<PPC64LinuxTargetObjectFile>();
195 }
196 
197 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
198                                                  const TargetOptions &Options) {
199   if (TT.isOSDarwin())
200     report_fatal_error("Darwin is no longer supported for PowerPC");
201 
202   if (Options.MCOptions.getABIName().startswith("elfv1"))
203     return PPCTargetMachine::PPC_ABI_ELFv1;
204   else if (Options.MCOptions.getABIName().startswith("elfv2"))
205     return PPCTargetMachine::PPC_ABI_ELFv2;
206 
207   assert(Options.MCOptions.getABIName().empty() &&
208          "Unknown target-abi option!");
209 
210   if (TT.isMacOSX())
211     return PPCTargetMachine::PPC_ABI_UNKNOWN;
212 
213   switch (TT.getArch()) {
214   case Triple::ppc64le:
215     return PPCTargetMachine::PPC_ABI_ELFv2;
216   case Triple::ppc64:
217     if (TT.getEnvironment() == llvm::Triple::ELFv2)
218       return PPCTargetMachine::PPC_ABI_ELFv2;
219     return PPCTargetMachine::PPC_ABI_ELFv1;
220   default:
221     return PPCTargetMachine::PPC_ABI_UNKNOWN;
222   }
223 }
224 
225 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
226                                            Optional<Reloc::Model> RM) {
227   if (RM.hasValue())
228     return *RM;
229 
230   // Darwin defaults to dynamic-no-pic.
231   if (TT.isOSDarwin())
232     return Reloc::DynamicNoPIC;
233 
234   // Big Endian PPC is PIC by default.
235   if (TT.getArch() == Triple::ppc64)
236     return Reloc::PIC_;
237 
238   // Rest are static by default.
239   return Reloc::Static;
240 }
241 
242 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
243                                                  Optional<CodeModel::Model> CM,
244                                                  bool JIT) {
245   if (CM) {
246     if (*CM == CodeModel::Tiny)
247       report_fatal_error("Target does not support the tiny CodeModel", false);
248     if (*CM == CodeModel::Kernel)
249       report_fatal_error("Target does not support the kernel CodeModel", false);
250     return *CM;
251   }
252 
253   if (JIT)
254     return CodeModel::Small;
255   if (TT.isOSAIX())
256     return CodeModel::Small;
257 
258   assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
259 
260   if (TT.isArch32Bit())
261     return CodeModel::Small;
262 
263   assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
264   return CodeModel::Medium;
265 }
266 
267 
268 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
269   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
270   ScheduleDAGMILive *DAG =
271     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
272                           std::make_unique<PPCPreRASchedStrategy>(C) :
273                           std::make_unique<GenericScheduler>(C));
274   // add DAG Mutations here.
275   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
276   return DAG;
277 }
278 
279 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
280   MachineSchedContext *C) {
281   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
282   ScheduleDAGMI *DAG =
283     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
284                       std::make_unique<PPCPostRASchedStrategy>(C) :
285                       std::make_unique<PostGenericScheduler>(C), true);
286   // add DAG Mutations here.
287   return DAG;
288 }
289 
290 // The FeatureString here is a little subtle. We are modifying the feature
291 // string with what are (currently) non-function specific overrides as it goes
292 // into the LLVMTargetMachine constructor and then using the stored value in the
293 // Subtarget constructor below it.
294 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
295                                    StringRef CPU, StringRef FS,
296                                    const TargetOptions &Options,
297                                    Optional<Reloc::Model> RM,
298                                    Optional<CodeModel::Model> CM,
299                                    CodeGenOpt::Level OL, bool JIT)
300     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
301                         computeFSAdditions(FS, OL, TT), Options,
302                         getEffectiveRelocModel(TT, RM),
303                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
304       TLOF(createTLOF(getTargetTriple())),
305       TargetABI(computeTargetABI(TT, Options)) {
306   initAsmInfo();
307 }
308 
309 PPCTargetMachine::~PPCTargetMachine() = default;
310 
311 const PPCSubtarget *
312 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
313   Attribute CPUAttr = F.getFnAttribute("target-cpu");
314   Attribute FSAttr = F.getFnAttribute("target-features");
315 
316   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
317                         ? CPUAttr.getValueAsString().str()
318                         : TargetCPU;
319   std::string FS = !FSAttr.hasAttribute(Attribute::None)
320                        ? FSAttr.getValueAsString().str()
321                        : TargetFS;
322 
323   // FIXME: This is related to the code below to reset the target options,
324   // we need to know whether or not the soft float flag is set on the
325   // function before we can generate a subtarget. We also need to use
326   // it as a key for the subtarget since that can be the only difference
327   // between two functions.
328   bool SoftFloat =
329       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
330   // If the soft float attribute is set on the function turn on the soft float
331   // subtarget feature.
332   if (SoftFloat)
333     FS += FS.empty() ? "-hard-float" : ",-hard-float";
334 
335   auto &I = SubtargetMap[CPU + FS];
336   if (!I) {
337     // This needs to be done before we create a new subtarget since any
338     // creation will depend on the TM and the code generation flags on the
339     // function that reside in TargetOptions.
340     resetTargetOptions(F);
341     I = std::make_unique<PPCSubtarget>(
342         TargetTriple, CPU,
343         // FIXME: It would be good to have the subtarget additions here
344         // not necessary. Anything that turns them on/off (overrides) ends
345         // up being put at the end of the feature string, but the defaults
346         // shouldn't require adding them. Fixing this means pulling Feature64Bit
347         // out of most of the target cpus in the .td file and making it set only
348         // as part of initialization via the TargetTriple.
349         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
350   }
351   return I.get();
352 }
353 
354 //===----------------------------------------------------------------------===//
355 // Pass Pipeline Configuration
356 //===----------------------------------------------------------------------===//
357 
358 namespace {
359 
360 /// PPC Code Generator Pass Configuration Options.
361 class PPCPassConfig : public TargetPassConfig {
362 public:
363   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
364     : TargetPassConfig(TM, PM) {
365     // At any optimization level above -O0 we use the Machine Scheduler and not
366     // the default Post RA List Scheduler.
367     if (TM.getOptLevel() != CodeGenOpt::None)
368       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
369   }
370 
371   PPCTargetMachine &getPPCTargetMachine() const {
372     return getTM<PPCTargetMachine>();
373   }
374 
375   void addIRPasses() override;
376   bool addPreISel() override;
377   bool addILPOpts() override;
378   bool addInstSelector() override;
379   void addMachineSSAOptimization() override;
380   void addPreRegAlloc() override;
381   void addPreSched2() override;
382   void addPreEmitPass() override;
383   ScheduleDAGInstrs *
384   createMachineScheduler(MachineSchedContext *C) const override {
385     return createPPCMachineScheduler(C);
386   }
387   ScheduleDAGInstrs *
388   createPostMachineScheduler(MachineSchedContext *C) const override {
389     return createPPCPostMachineScheduler(C);
390   }
391 };
392 
393 } // end anonymous namespace
394 
395 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
396   return new PPCPassConfig(*this, PM);
397 }
398 
399 void PPCPassConfig::addIRPasses() {
400   if (TM->getOptLevel() != CodeGenOpt::None)
401     addPass(createPPCBoolRetToIntPass());
402   addPass(createAtomicExpandPass());
403 
404   // For the BG/Q (or if explicitly requested), add explicit data prefetch
405   // intrinsics.
406   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
407                         getOptLevel() != CodeGenOpt::None;
408   if (EnablePrefetch.getNumOccurrences() > 0)
409     UsePrefetching = EnablePrefetch;
410   if (UsePrefetching)
411     addPass(createLoopDataPrefetchPass());
412 
413   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
414     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
415     // and lower a GEP with multiple indices to either arithmetic operations or
416     // multiple GEPs with single index.
417     addPass(createSeparateConstOffsetFromGEPPass(true));
418     // Call EarlyCSE pass to find and remove subexpressions in the lowered
419     // result.
420     addPass(createEarlyCSEPass());
421     // Do loop invariant code motion in case part of the lowered result is
422     // invariant.
423     addPass(createLICMPass());
424   }
425 
426   TargetPassConfig::addIRPasses();
427 }
428 
429 bool PPCPassConfig::addPreISel() {
430   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
431     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
432 
433   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
434     addPass(createHardwareLoopsPass());
435 
436   return false;
437 }
438 
439 bool PPCPassConfig::addILPOpts() {
440   addPass(&EarlyIfConverterID);
441 
442   if (EnableMachineCombinerPass)
443     addPass(&MachineCombinerID);
444 
445   return true;
446 }
447 
448 bool PPCPassConfig::addInstSelector() {
449   // Install an instruction selector.
450   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
451 
452 #ifndef NDEBUG
453   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
454     addPass(createPPCCTRLoopsVerify());
455 #endif
456 
457   addPass(createPPCVSXCopyPass());
458   return false;
459 }
460 
461 void PPCPassConfig::addMachineSSAOptimization() {
462   // PPCBranchCoalescingPass need to be done before machine sinking
463   // since it merges empty blocks.
464   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
465     addPass(createPPCBranchCoalescingPass());
466   TargetPassConfig::addMachineSSAOptimization();
467   // For little endian, remove where possible the vector swap instructions
468   // introduced at code generation to normalize vector element order.
469   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
470       !DisableVSXSwapRemoval)
471     addPass(createPPCVSXSwapRemovalPass());
472   // Reduce the number of cr-logical ops.
473   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
474     addPass(createPPCReduceCRLogicalsPass());
475   // Target-specific peephole cleanups performed after instruction
476   // selection.
477   if (!DisableMIPeephole) {
478     addPass(createPPCMIPeepholePass());
479     addPass(&DeadMachineInstructionElimID);
480   }
481 }
482 
483 void PPCPassConfig::addPreRegAlloc() {
484   if (getOptLevel() != CodeGenOpt::None) {
485     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
486     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
487                &PPCVSXFMAMutateID);
488   }
489 
490   // FIXME: We probably don't need to run these for -fPIE.
491   if (getPPCTargetMachine().isPositionIndependent()) {
492     // FIXME: LiveVariables should not be necessary here!
493     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
494     // LiveVariables. This (unnecessary) dependency has been removed now,
495     // however a stage-2 clang build fails without LiveVariables computed here.
496     addPass(&LiveVariablesID, false);
497     addPass(createPPCTLSDynamicCallPass());
498   }
499   if (EnableExtraTOCRegDeps)
500     addPass(createPPCTOCRegDepsPass());
501 
502   if (getOptLevel() != CodeGenOpt::None)
503     addPass(&MachinePipelinerID);
504 }
505 
506 void PPCPassConfig::addPreSched2() {
507   if (getOptLevel() != CodeGenOpt::None) {
508     addPass(&IfConverterID);
509 
510     // This optimization must happen after anything that might do store-to-load
511     // forwarding. Here we're after RA (and, thus, when spills are inserted)
512     // but before post-RA scheduling.
513     if (!DisableQPXLoadSplat)
514       addPass(createPPCQPXLoadSplatPass());
515   }
516 }
517 
518 void PPCPassConfig::addPreEmitPass() {
519   addPass(createPPCPreEmitPeepholePass());
520   addPass(createPPCExpandISELPass());
521 
522   if (getOptLevel() != CodeGenOpt::None)
523     addPass(createPPCEarlyReturnPass(), false);
524   // Must run branch selection immediately preceding the asm printer.
525   addPass(createPPCBranchSelectionPass(), false);
526 }
527 
528 TargetTransformInfo
529 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
530   return TargetTransformInfo(PPCTTIImpl(this, F));
531 }
532 
533 static MachineSchedRegistry
534 PPCPreRASchedRegistry("ppc-prera",
535                       "Run PowerPC PreRA specific scheduler",
536                       createPPCMachineScheduler);
537 
538 static MachineSchedRegistry
539 PPCPostRASchedRegistry("ppc-postra",
540                        "Run PowerPC PostRA specific scheduler",
541                        createPPCPostMachineScheduler);
542