1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPC.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 using namespace llvm;
23 
24 extern "C" void LLVMInitializePowerPCTarget() {
25   // Register the targets
26   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
27   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
28 }
29 
30 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
31                                    StringRef CPU, StringRef FS,
32                                    const TargetOptions &Options,
33                                    Reloc::Model RM, CodeModel::Model CM,
34                                    CodeGenOpt::Level OL,
35                                    bool is64Bit)
36   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
37     Subtarget(TT, CPU, FS, is64Bit),
38     DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
39     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
40     TLInfo(*this), TSInfo(*this),
41     InstrItins(Subtarget.getInstrItineraryData()) {
42 }
43 
44 void PPC32TargetMachine::anchor() { }
45 
46 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
47                                        StringRef CPU, StringRef FS,
48                                        const TargetOptions &Options,
49                                        Reloc::Model RM, CodeModel::Model CM,
50                                        CodeGenOpt::Level OL)
51   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
52 }
53 
54 void PPC64TargetMachine::anchor() { }
55 
56 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
57                                        StringRef CPU,  StringRef FS,
58                                        const TargetOptions &Options,
59                                        Reloc::Model RM, CodeModel::Model CM,
60                                        CodeGenOpt::Level OL)
61   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
62 }
63 
64 
65 //===----------------------------------------------------------------------===//
66 // Pass Pipeline Configuration
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 /// PPC Code Generator Pass Configuration Options.
71 class PPCPassConfig : public TargetPassConfig {
72 public:
73   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
74     : TargetPassConfig(TM, PM) {}
75 
76   PPCTargetMachine &getPPCTargetMachine() const {
77     return getTM<PPCTargetMachine>();
78   }
79 
80   virtual bool addInstSelector();
81   virtual bool getEnableTailMergeDefault() const;
82   virtual bool addPreEmitPass();
83 };
84 } // namespace
85 
86 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
87   return new PPCPassConfig(this, PM);
88 }
89 
90 bool PPCPassConfig::addInstSelector() {
91   // Install an instruction selector.
92   PM.add(createPPCISelDag(getPPCTargetMachine()));
93   return false;
94 }
95 
96 /// Override this for PowerPC.  Tail merging happily breaks up instruction issue
97 /// groups, which typically degrades performance.
98 bool PPCPassConfig::getEnableTailMergeDefault() const { return false; }
99 
100 bool PPCPassConfig::addPreEmitPass() {
101   // Must run branch selection immediately preceding the asm printer.
102   PM.add(createPPCBranchSelectionPass());
103   return false;
104 }
105 
106 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
107                                       JITCodeEmitter &JCE) {
108   // FIXME: This should be moved to TargetJITInfo!!
109   if (Subtarget.isPPC64())
110     // Temporary workaround for the inability of PPC64 JIT to handle jump
111     // tables.
112     Options.DisableJumpTables = true;
113 
114   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
115   // writing?
116   Subtarget.SetJITMode();
117 
118   // Machine code emitter pass for PowerPC.
119   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
120 
121   return false;
122 }
123