1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "TargetInfo/PowerPCTargetInfo.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Pass.h"
33 #include "llvm/Support/CodeGen.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Transforms/Scalar.h"
39 #include <cassert>
40 #include <memory>
41 #include <string>
42 
43 using namespace llvm;
44 
45 
46 static cl::opt<bool>
47     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
48                            cl::desc("enable coalescing of duplicate branches for PPC"));
49 static cl::
50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
51                         cl::desc("Disable CTR loops for PPC"));
52 
53 static cl::
54 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
55                             cl::desc("Disable PPC loop preinc prep"));
56 
57 static cl::opt<bool>
58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
59   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
60 
61 static cl::
62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
63                                 cl::desc("Disable VSX Swap Removal for PPC"));
64 
65 static cl::
66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
67                               cl::desc("Disable QPX load splat simplification"));
68 
69 static cl::
70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
71                             cl::desc("Disable machine peepholes for PPC"));
72 
73 static cl::opt<bool>
74 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
75              cl::desc("Enable optimizations on complex GEPs"),
76              cl::init(true));
77 
78 static cl::opt<bool>
79 EnablePrefetch("enable-ppc-prefetching",
80                   cl::desc("disable software prefetching on PPC"),
81                   cl::init(false), cl::Hidden);
82 
83 static cl::opt<bool>
84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
85                       cl::desc("Add extra TOC register dependencies"),
86                       cl::init(true), cl::Hidden);
87 
88 static cl::opt<bool>
89 EnableMachineCombinerPass("ppc-machine-combiner",
90                           cl::desc("Enable the machine combiner pass"),
91                           cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool>
94   ReduceCRLogical("ppc-reduce-cr-logicals",
95                   cl::desc("Expand eligible cr-logical binary ops to branches"),
96                   cl::init(false), cl::Hidden);
97 extern "C" void LLVMInitializePowerPCTarget() {
98   // Register the targets
99   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
100   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
101   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
102 
103   PassRegistry &PR = *PassRegistry::getPassRegistry();
104   initializePPCCTRLoopsPass(PR);
105 #ifndef NDEBUG
106   initializePPCCTRLoopsVerifyPass(PR);
107 #endif
108   initializePPCLoopPreIncPrepPass(PR);
109   initializePPCTOCRegDepsPass(PR);
110   initializePPCEarlyReturnPass(PR);
111   initializePPCVSXCopyPass(PR);
112   initializePPCVSXFMAMutatePass(PR);
113   initializePPCVSXSwapRemovalPass(PR);
114   initializePPCReduceCRLogicalsPass(PR);
115   initializePPCBSelPass(PR);
116   initializePPCBranchCoalescingPass(PR);
117   initializePPCQPXLoadSplatPass(PR);
118   initializePPCBoolRetToIntPass(PR);
119   initializePPCExpandISELPass(PR);
120   initializePPCPreEmitPeepholePass(PR);
121   initializePPCTLSDynamicCallPass(PR);
122   initializePPCMIPeepholePass(PR);
123 }
124 
125 /// Return the datalayout string of a subtarget.
126 static std::string getDataLayoutString(const Triple &T) {
127   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
128   std::string Ret;
129 
130   // Most PPC* platforms are big endian, PPC64LE is little endian.
131   if (T.getArch() == Triple::ppc64le)
132     Ret = "e";
133   else
134     Ret = "E";
135 
136   Ret += DataLayout::getManglingComponent(T);
137 
138   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
139   // pointers.
140   if (!is64Bit || T.getOS() == Triple::Lv2)
141     Ret += "-p:32:32";
142 
143   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
144   // documentation are wrong; these are correct (i.e. "what gcc does").
145   if (is64Bit || !T.isOSDarwin())
146     Ret += "-i64:64";
147   else
148     Ret += "-f64:32:64";
149 
150   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
151   if (is64Bit)
152     Ret += "-n32:64";
153   else
154     Ret += "-n32";
155 
156   return Ret;
157 }
158 
159 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
160                                       const Triple &TT) {
161   std::string FullFS = FS;
162 
163   // Make sure 64-bit features are available when CPUname is generic
164   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
165     if (!FullFS.empty())
166       FullFS = "+64bit," + FullFS;
167     else
168       FullFS = "+64bit";
169   }
170 
171   if (OL >= CodeGenOpt::Default) {
172     if (!FullFS.empty())
173       FullFS = "+crbits," + FullFS;
174     else
175       FullFS = "+crbits";
176   }
177 
178   if (OL != CodeGenOpt::None) {
179     if (!FullFS.empty())
180       FullFS = "+invariant-function-descriptors," + FullFS;
181     else
182       FullFS = "+invariant-function-descriptors";
183   }
184 
185   return FullFS;
186 }
187 
188 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
189   // If it isn't a Mach-O file then it's going to be a linux ELF
190   // object file.
191   if (TT.isOSDarwin())
192     return llvm::make_unique<TargetLoweringObjectFileMachO>();
193 
194   return llvm::make_unique<PPC64LinuxTargetObjectFile>();
195 }
196 
197 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
198                                                  const TargetOptions &Options) {
199   if (TT.isOSDarwin())
200     report_fatal_error("Darwin is no longer supported for PowerPC");
201 
202   if (Options.MCOptions.getABIName().startswith("elfv1"))
203     return PPCTargetMachine::PPC_ABI_ELFv1;
204   else if (Options.MCOptions.getABIName().startswith("elfv2"))
205     return PPCTargetMachine::PPC_ABI_ELFv2;
206 
207   assert(Options.MCOptions.getABIName().empty() &&
208          "Unknown target-abi option!");
209 
210   if (TT.isMacOSX())
211     return PPCTargetMachine::PPC_ABI_UNKNOWN;
212 
213   switch (TT.getArch()) {
214   case Triple::ppc64le:
215     return PPCTargetMachine::PPC_ABI_ELFv2;
216   case Triple::ppc64:
217     return PPCTargetMachine::PPC_ABI_ELFv1;
218   default:
219     return PPCTargetMachine::PPC_ABI_UNKNOWN;
220   }
221 }
222 
223 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
224                                            Optional<Reloc::Model> RM) {
225   if (RM.hasValue())
226     return *RM;
227 
228   // Darwin defaults to dynamic-no-pic.
229   if (TT.isOSDarwin())
230     return Reloc::DynamicNoPIC;
231 
232   // Big Endian PPC is PIC by default.
233   if (TT.getArch() == Triple::ppc64)
234     return Reloc::PIC_;
235 
236   // Rest are static by default.
237   return Reloc::Static;
238 }
239 
240 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
241                                                  Optional<CodeModel::Model> CM,
242                                                  bool JIT) {
243   if (CM) {
244     if (*CM == CodeModel::Tiny)
245       report_fatal_error("Target does not support the tiny CodeModel");
246     if (*CM == CodeModel::Kernel)
247       report_fatal_error("Target does not support the kernel CodeModel");
248     return *CM;
249   }
250   if (!TT.isOSDarwin() && !JIT &&
251       (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
252     return CodeModel::Medium;
253   return CodeModel::Small;
254 }
255 
256 
257 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
258   ScheduleDAGMILive *DAG =
259     new ScheduleDAGMILive(C, llvm::make_unique<PPCPreRASchedStrategy>(C));
260   // add DAG Mutations here.
261   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
262   return DAG;
263 }
264 
265 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
266   MachineSchedContext *C) {
267   ScheduleDAGMI *DAG =
268     new ScheduleDAGMI(C, llvm::make_unique<PPCPostRASchedStrategy>(C), true);
269   // add DAG Mutations here.
270   return DAG;
271 }
272 
273 // The FeatureString here is a little subtle. We are modifying the feature
274 // string with what are (currently) non-function specific overrides as it goes
275 // into the LLVMTargetMachine constructor and then using the stored value in the
276 // Subtarget constructor below it.
277 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
278                                    StringRef CPU, StringRef FS,
279                                    const TargetOptions &Options,
280                                    Optional<Reloc::Model> RM,
281                                    Optional<CodeModel::Model> CM,
282                                    CodeGenOpt::Level OL, bool JIT)
283     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
284                         computeFSAdditions(FS, OL, TT), Options,
285                         getEffectiveRelocModel(TT, RM),
286                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
287       TLOF(createTLOF(getTargetTriple())),
288       TargetABI(computeTargetABI(TT, Options)) {
289   initAsmInfo();
290 }
291 
292 PPCTargetMachine::~PPCTargetMachine() = default;
293 
294 const PPCSubtarget *
295 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
296   Attribute CPUAttr = F.getFnAttribute("target-cpu");
297   Attribute FSAttr = F.getFnAttribute("target-features");
298 
299   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
300                         ? CPUAttr.getValueAsString().str()
301                         : TargetCPU;
302   std::string FS = !FSAttr.hasAttribute(Attribute::None)
303                        ? FSAttr.getValueAsString().str()
304                        : TargetFS;
305 
306   // FIXME: This is related to the code below to reset the target options,
307   // we need to know whether or not the soft float flag is set on the
308   // function before we can generate a subtarget. We also need to use
309   // it as a key for the subtarget since that can be the only difference
310   // between two functions.
311   bool SoftFloat =
312       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
313   // If the soft float attribute is set on the function turn on the soft float
314   // subtarget feature.
315   if (SoftFloat)
316     FS += FS.empty() ? "-hard-float" : ",-hard-float";
317 
318   auto &I = SubtargetMap[CPU + FS];
319   if (!I) {
320     // This needs to be done before we create a new subtarget since any
321     // creation will depend on the TM and the code generation flags on the
322     // function that reside in TargetOptions.
323     resetTargetOptions(F);
324     I = llvm::make_unique<PPCSubtarget>(
325         TargetTriple, CPU,
326         // FIXME: It would be good to have the subtarget additions here
327         // not necessary. Anything that turns them on/off (overrides) ends
328         // up being put at the end of the feature string, but the defaults
329         // shouldn't require adding them. Fixing this means pulling Feature64Bit
330         // out of most of the target cpus in the .td file and making it set only
331         // as part of initialization via the TargetTriple.
332         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
333   }
334   return I.get();
335 }
336 
337 //===----------------------------------------------------------------------===//
338 // Pass Pipeline Configuration
339 //===----------------------------------------------------------------------===//
340 
341 namespace {
342 
343 /// PPC Code Generator Pass Configuration Options.
344 class PPCPassConfig : public TargetPassConfig {
345 public:
346   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
347     : TargetPassConfig(TM, PM) {
348     // At any optimization level above -O0 we use the Machine Scheduler and not
349     // the default Post RA List Scheduler.
350     if (TM.getOptLevel() != CodeGenOpt::None)
351       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
352   }
353 
354   PPCTargetMachine &getPPCTargetMachine() const {
355     return getTM<PPCTargetMachine>();
356   }
357 
358   void addIRPasses() override;
359   bool addPreISel() override;
360   bool addILPOpts() override;
361   bool addInstSelector() override;
362   void addMachineSSAOptimization() override;
363   void addPreRegAlloc() override;
364   void addPreSched2() override;
365   void addPreEmitPass() override;
366   ScheduleDAGInstrs *
367   createMachineScheduler(MachineSchedContext *C) const override {
368     const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
369     if (ST.usePPCPreRASchedStrategy())
370       return createPPCMachineScheduler(C);
371     return nullptr;
372   }
373   ScheduleDAGInstrs *
374   createPostMachineScheduler(MachineSchedContext *C) const override {
375     const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
376     if (ST.usePPCPostRASchedStrategy())
377       return createPPCPostMachineScheduler(C);
378     return nullptr;
379   }
380 };
381 
382 } // end anonymous namespace
383 
384 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
385   return new PPCPassConfig(*this, PM);
386 }
387 
388 void PPCPassConfig::addIRPasses() {
389   if (TM->getOptLevel() != CodeGenOpt::None)
390     addPass(createPPCBoolRetToIntPass());
391   addPass(createAtomicExpandPass());
392 
393   // For the BG/Q (or if explicitly requested), add explicit data prefetch
394   // intrinsics.
395   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
396                         getOptLevel() != CodeGenOpt::None;
397   if (EnablePrefetch.getNumOccurrences() > 0)
398     UsePrefetching = EnablePrefetch;
399   if (UsePrefetching)
400     addPass(createLoopDataPrefetchPass());
401 
402   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
403     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
404     // and lower a GEP with multiple indices to either arithmetic operations or
405     // multiple GEPs with single index.
406     addPass(createSeparateConstOffsetFromGEPPass(true));
407     // Call EarlyCSE pass to find and remove subexpressions in the lowered
408     // result.
409     addPass(createEarlyCSEPass());
410     // Do loop invariant code motion in case part of the lowered result is
411     // invariant.
412     addPass(createLICMPass());
413   }
414 
415   TargetPassConfig::addIRPasses();
416 }
417 
418 bool PPCPassConfig::addPreISel() {
419   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
420     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
421 
422   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
423     addPass(createPPCCTRLoops());
424 
425   return false;
426 }
427 
428 bool PPCPassConfig::addILPOpts() {
429   addPass(&EarlyIfConverterID);
430 
431   if (EnableMachineCombinerPass)
432     addPass(&MachineCombinerID);
433 
434   return true;
435 }
436 
437 bool PPCPassConfig::addInstSelector() {
438   // Install an instruction selector.
439   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
440 
441 #ifndef NDEBUG
442   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
443     addPass(createPPCCTRLoopsVerify());
444 #endif
445 
446   addPass(createPPCVSXCopyPass());
447   return false;
448 }
449 
450 void PPCPassConfig::addMachineSSAOptimization() {
451   // PPCBranchCoalescingPass need to be done before machine sinking
452   // since it merges empty blocks.
453   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
454     addPass(createPPCBranchCoalescingPass());
455   TargetPassConfig::addMachineSSAOptimization();
456   // For little endian, remove where possible the vector swap instructions
457   // introduced at code generation to normalize vector element order.
458   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
459       !DisableVSXSwapRemoval)
460     addPass(createPPCVSXSwapRemovalPass());
461   // Reduce the number of cr-logical ops.
462   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
463     addPass(createPPCReduceCRLogicalsPass());
464   // Target-specific peephole cleanups performed after instruction
465   // selection.
466   if (!DisableMIPeephole) {
467     addPass(createPPCMIPeepholePass());
468     addPass(&DeadMachineInstructionElimID);
469   }
470 }
471 
472 void PPCPassConfig::addPreRegAlloc() {
473   if (getOptLevel() != CodeGenOpt::None) {
474     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
475     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
476                &PPCVSXFMAMutateID);
477   }
478 
479   // FIXME: We probably don't need to run these for -fPIE.
480   if (getPPCTargetMachine().isPositionIndependent()) {
481     // FIXME: LiveVariables should not be necessary here!
482     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
483     // LiveVariables. This (unnecessary) dependency has been removed now,
484     // however a stage-2 clang build fails without LiveVariables computed here.
485     addPass(&LiveVariablesID, false);
486     addPass(createPPCTLSDynamicCallPass());
487   }
488   if (EnableExtraTOCRegDeps)
489     addPass(createPPCTOCRegDepsPass());
490 }
491 
492 void PPCPassConfig::addPreSched2() {
493   if (getOptLevel() != CodeGenOpt::None) {
494     addPass(&IfConverterID);
495 
496     // This optimization must happen after anything that might do store-to-load
497     // forwarding. Here we're after RA (and, thus, when spills are inserted)
498     // but before post-RA scheduling.
499     if (!DisableQPXLoadSplat)
500       addPass(createPPCQPXLoadSplatPass());
501   }
502 }
503 
504 void PPCPassConfig::addPreEmitPass() {
505   addPass(createPPCPreEmitPeepholePass());
506   addPass(createPPCExpandISELPass());
507 
508   if (getOptLevel() != CodeGenOpt::None)
509     addPass(createPPCEarlyReturnPass(), false);
510   // Must run branch selection immediately preceding the asm printer.
511   addPass(createPPCBranchSelectionPass(), false);
512 }
513 
514 TargetTransformInfo
515 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
516   return TargetTransformInfo(PPCTTIImpl(this, F));
517 }
518 
519 static MachineSchedRegistry
520 PPCPreRASchedRegistry("ppc-prera",
521                       "Run PowerPC PreRA specific scheduler",
522                       createPPCMachineScheduler);
523 
524 static MachineSchedRegistry
525 PPCPostRASchedRegistry("ppc-postra",
526                        "Run PowerPC PostRA specific scheduler",
527                        createPPCPostMachineScheduler);
528