1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31                         cl::desc("Disable CTR loops for PPC"));
32 
33 static cl::
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35                             cl::desc("Disable PPC loop preinc prep"));
36 
37 static cl::opt<bool>
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
40 
41 static cl::
42 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
43                                 cl::desc("Disable VSX Swap Removal for PPC"));
44 
45 static cl::opt<bool>
46 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
47              cl::desc("Enable optimizations on complex GEPs"),
48              cl::init(true));
49 
50 static cl::opt<bool>
51 EnablePrefetch("enable-ppc-prefetching",
52                   cl::desc("disable software prefetching on PPC"),
53                   cl::init(false), cl::Hidden);
54 
55 static cl::opt<bool>
56 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
57                       cl::desc("Add extra TOC register dependencies"),
58                       cl::init(true), cl::Hidden);
59 
60 extern "C" void LLVMInitializePowerPCTarget() {
61   // Register the targets
62   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
63   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
64   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
65 }
66 
67 /// Return the datalayout string of a subtarget.
68 static std::string getDataLayoutString(const Triple &T) {
69   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
70   std::string Ret;
71 
72   // Most PPC* platforms are big endian, PPC64LE is little endian.
73   if (T.getArch() == Triple::ppc64le)
74     Ret = "e";
75   else
76     Ret = "E";
77 
78   Ret += DataLayout::getManglingComponent(T);
79 
80   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
81   // pointers.
82   if (!is64Bit || T.getOS() == Triple::Lv2)
83     Ret += "-p:32:32";
84 
85   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
86   // documentation are wrong; these are correct (i.e. "what gcc does").
87   if (is64Bit || !T.isOSDarwin())
88     Ret += "-i64:64";
89   else
90     Ret += "-f64:32:64";
91 
92   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
93   if (is64Bit)
94     Ret += "-n32:64";
95   else
96     Ret += "-n32";
97 
98   return Ret;
99 }
100 
101 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
102                                       const Triple &TT) {
103   std::string FullFS = FS;
104 
105   // Make sure 64-bit features are available when CPUname is generic
106   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
107     if (!FullFS.empty())
108       FullFS = "+64bit," + FullFS;
109     else
110       FullFS = "+64bit";
111   }
112 
113   if (OL >= CodeGenOpt::Default) {
114     if (!FullFS.empty())
115       FullFS = "+crbits," + FullFS;
116     else
117       FullFS = "+crbits";
118   }
119 
120   if (OL != CodeGenOpt::None) {
121      if (!FullFS.empty())
122       FullFS = "+invariant-function-descriptors," + FullFS;
123     else
124       FullFS = "+invariant-function-descriptors";
125   }
126 
127   return FullFS;
128 }
129 
130 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
131   // If it isn't a Mach-O file then it's going to be a linux ELF
132   // object file.
133   if (TT.isOSDarwin())
134     return make_unique<TargetLoweringObjectFileMachO>();
135 
136   return make_unique<PPC64LinuxTargetObjectFile>();
137 }
138 
139 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
140                                                  const TargetOptions &Options) {
141   if (Options.MCOptions.getABIName().startswith("elfv1"))
142     return PPCTargetMachine::PPC_ABI_ELFv1;
143   else if (Options.MCOptions.getABIName().startswith("elfv2"))
144     return PPCTargetMachine::PPC_ABI_ELFv2;
145 
146   assert(Options.MCOptions.getABIName().empty() &&
147 	 "Unknown target-abi option!");
148 
149   if (!TT.isMacOSX()) {
150     switch (TT.getArch()) {
151     case Triple::ppc64le:
152       return PPCTargetMachine::PPC_ABI_ELFv2;
153     case Triple::ppc64:
154       return PPCTargetMachine::PPC_ABI_ELFv1;
155     default:
156       // Fallthrough.
157       ;
158     }
159   }
160   return PPCTargetMachine::PPC_ABI_UNKNOWN;
161 }
162 
163 // The FeatureString here is a little subtle. We are modifying the feature string
164 // with what are (currently) non-function specific overrides as it goes into the
165 // LLVMTargetMachine constructor and then using the stored value in the
166 // Subtarget constructor below it.
167 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
168                                    StringRef CPU, StringRef FS,
169                                    const TargetOptions &Options,
170                                    Reloc::Model RM, CodeModel::Model CM,
171                                    CodeGenOpt::Level OL)
172     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
173                         computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
174       TLOF(createTLOF(getTargetTriple())),
175       TargetABI(computeTargetABI(TT, Options)) {
176   initAsmInfo();
177 }
178 
179 PPCTargetMachine::~PPCTargetMachine() {}
180 
181 void PPC32TargetMachine::anchor() { }
182 
183 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
184                                        StringRef CPU, StringRef FS,
185                                        const TargetOptions &Options,
186                                        Reloc::Model RM, CodeModel::Model CM,
187                                        CodeGenOpt::Level OL)
188     : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
189 
190 void PPC64TargetMachine::anchor() { }
191 
192 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
193                                        StringRef CPU, StringRef FS,
194                                        const TargetOptions &Options,
195                                        Reloc::Model RM, CodeModel::Model CM,
196                                        CodeGenOpt::Level OL)
197     : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
198 
199 const PPCSubtarget *
200 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
201   Attribute CPUAttr = F.getFnAttribute("target-cpu");
202   Attribute FSAttr = F.getFnAttribute("target-features");
203 
204   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
205                         ? CPUAttr.getValueAsString().str()
206                         : TargetCPU;
207   std::string FS = !FSAttr.hasAttribute(Attribute::None)
208                        ? FSAttr.getValueAsString().str()
209                        : TargetFS;
210 
211   auto &I = SubtargetMap[CPU + FS];
212   if (!I) {
213     // This needs to be done before we create a new subtarget since any
214     // creation will depend on the TM and the code generation flags on the
215     // function that reside in TargetOptions.
216     resetTargetOptions(F);
217     I = llvm::make_unique<PPCSubtarget>(
218         TargetTriple, CPU,
219         // FIXME: It would be good to have the subtarget additions here
220         // not necessary. Anything that turns them on/off (overrides) ends
221         // up being put at the end of the feature string, but the defaults
222         // shouldn't require adding them. Fixing this means pulling Feature64Bit
223         // out of most of the target cpus in the .td file and making it set only
224         // as part of initialization via the TargetTriple.
225         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
226   }
227   return I.get();
228 }
229 
230 //===----------------------------------------------------------------------===//
231 // Pass Pipeline Configuration
232 //===----------------------------------------------------------------------===//
233 
234 namespace {
235 /// PPC Code Generator Pass Configuration Options.
236 class PPCPassConfig : public TargetPassConfig {
237 public:
238   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
239     : TargetPassConfig(TM, PM) {}
240 
241   PPCTargetMachine &getPPCTargetMachine() const {
242     return getTM<PPCTargetMachine>();
243   }
244 
245   void addIRPasses() override;
246   bool addPreISel() override;
247   bool addILPOpts() override;
248   bool addInstSelector() override;
249   void addMachineSSAOptimization() override;
250   void addPreRegAlloc() override;
251   void addPreSched2() override;
252   void addPreEmitPass() override;
253 };
254 } // namespace
255 
256 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
257   return new PPCPassConfig(this, PM);
258 }
259 
260 void PPCPassConfig::addIRPasses() {
261   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
262 
263   // For the BG/Q (or if explicitly requested), add explicit data prefetch
264   // intrinsics.
265   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
266                         getOptLevel() != CodeGenOpt::None;
267   if (EnablePrefetch.getNumOccurrences() > 0)
268     UsePrefetching = EnablePrefetch;
269   if (UsePrefetching)
270     addPass(createPPCLoopDataPrefetchPass());
271 
272   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
273     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
274     // and lower a GEP with multiple indices to either arithmetic operations or
275     // multiple GEPs with single index.
276     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
277     // Call EarlyCSE pass to find and remove subexpressions in the lowered
278     // result.
279     addPass(createEarlyCSEPass());
280     // Do loop invariant code motion in case part of the lowered result is
281     // invariant.
282     addPass(createLICMPass());
283   }
284 
285   TargetPassConfig::addIRPasses();
286 }
287 
288 bool PPCPassConfig::addPreISel() {
289   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
290     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
291 
292   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
293     addPass(createPPCCTRLoops(getPPCTargetMachine()));
294 
295   return false;
296 }
297 
298 bool PPCPassConfig::addILPOpts() {
299   addPass(&EarlyIfConverterID);
300   return true;
301 }
302 
303 bool PPCPassConfig::addInstSelector() {
304   // Install an instruction selector.
305   addPass(createPPCISelDag(getPPCTargetMachine()));
306 
307 #ifndef NDEBUG
308   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
309     addPass(createPPCCTRLoopsVerify());
310 #endif
311 
312   addPass(createPPCVSXCopyPass());
313   return false;
314 }
315 
316 void PPCPassConfig::addMachineSSAOptimization() {
317   TargetPassConfig::addMachineSSAOptimization();
318   // For little endian, remove where possible the vector swap instructions
319   // introduced at code generation to normalize vector element order.
320   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
321       !DisableVSXSwapRemoval)
322     addPass(createPPCVSXSwapRemovalPass());
323 }
324 
325 void PPCPassConfig::addPreRegAlloc() {
326   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
327   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
328              &PPCVSXFMAMutateID);
329   if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
330     addPass(createPPCTLSDynamicCallPass());
331   if (EnableExtraTOCRegDeps)
332     addPass(createPPCTOCRegDepsPass());
333 }
334 
335 void PPCPassConfig::addPreSched2() {
336   if (getOptLevel() != CodeGenOpt::None)
337     addPass(&IfConverterID);
338 }
339 
340 void PPCPassConfig::addPreEmitPass() {
341   if (getOptLevel() != CodeGenOpt::None)
342     addPass(createPPCEarlyReturnPass(), false);
343   // Must run branch selection immediately preceding the asm printer.
344   addPass(createPPCBranchSelectionPass(), false);
345 }
346 
347 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
348   return TargetIRAnalysis(
349       [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
350 }
351