1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/Utils.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/IR/Constants.h"
24 
25 #define DEBUG_TYPE "globalisel-utils"
26 
27 using namespace llvm;
28 
29 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
30                                    const TargetInstrInfo &TII,
31                                    const RegisterBankInfo &RBI,
32                                    MachineInstr &InsertPt, unsigned Reg,
33                                    const TargetRegisterClass &RegClass) {
34   if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
35     unsigned NewReg = MRI.createVirtualRegister(&RegClass);
36     BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
37             TII.get(TargetOpcode::COPY), NewReg)
38         .addReg(Reg);
39     return NewReg;
40   }
41 
42   return Reg;
43 }
44 
45 
46 unsigned llvm::constrainOperandRegClass(
47     const MachineFunction &MF, const TargetRegisterInfo &TRI,
48     MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
49     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
50     unsigned Reg, unsigned OpIdx) {
51   // Assume physical registers are properly constrained.
52   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
53          "PhysReg not implemented");
54 
55   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
56   return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
57 }
58 
59 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
60                                             const TargetInstrInfo &TII,
61                                             const TargetRegisterInfo &TRI,
62                                             const RegisterBankInfo &RBI) {
63   MachineBasicBlock &MBB = *I.getParent();
64   MachineFunction &MF = *MBB.getParent();
65   MachineRegisterInfo &MRI = MF.getRegInfo();
66 
67   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
68     MachineOperand &MO = I.getOperand(OpI);
69 
70     // There's nothing to be done on non-register operands.
71     if (!MO.isReg())
72       continue;
73 
74     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
75     assert(MO.isReg() && "Unsupported non-reg operand");
76 
77     unsigned Reg = MO.getReg();
78     // Physical registers don't need to be constrained.
79     if (TRI.isPhysicalRegister(Reg))
80       continue;
81 
82     // Register operands with a value of 0 (e.g. predicate operands) don't need
83     // to be constrained.
84     if (Reg == 0)
85       continue;
86 
87     // If the operand is a vreg, we should constrain its regclass, and only
88     // insert COPYs if that's impossible.
89     // constrainOperandRegClass does that for us.
90     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
91                                        Reg, OpI));
92 
93     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
94     // done.
95     if (MO.isUse()) {
96       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
97       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
98         I.tieOperands(DefIdx, OpI);
99     }
100   }
101   return true;
102 }
103 
104 bool llvm::isTriviallyDead(const MachineInstr &MI,
105                            const MachineRegisterInfo &MRI) {
106   // If we can move an instruction, we can remove it.  Otherwise, it has
107   // a side-effect of some sort.
108   bool SawStore = false;
109   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
110     return false;
111 
112   // Instructions without side-effects are dead iff they only define dead vregs.
113   for (auto &MO : MI.operands()) {
114     if (!MO.isReg() || !MO.isDef())
115       continue;
116 
117     unsigned Reg = MO.getReg();
118     if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
119         !MRI.use_nodbg_empty(Reg))
120       return false;
121   }
122   return true;
123 }
124 
125 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
126                               MachineOptimizationRemarkEmitter &MORE,
127                               MachineOptimizationRemarkMissed &R) {
128   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
129 
130   // Print the function name explicitly if we don't have a debug location (which
131   // makes the diagnostic less useful) or if we're going to emit a raw error.
132   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
133     R << (" (in function: " + MF.getName() + ")").str();
134 
135   if (TPC.isGlobalISelAbortEnabled())
136     report_fatal_error(R.getMsg());
137   else
138     MORE.emit(R);
139 }
140 
141 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
142                               MachineOptimizationRemarkEmitter &MORE,
143                               const char *PassName, StringRef Msg,
144                               const MachineInstr &MI) {
145   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
146                                     MI.getDebugLoc(), MI.getParent());
147   R << Msg;
148   // Printing MI is expensive;  only do it if expensive remarks are enabled.
149   if (MORE.allowExtraAnalysis(PassName))
150     R << ": " << ore::MNV("Inst", MI);
151   reportGISelFailure(MF, TPC, MORE, R);
152 }
153 
154 Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
155                                            const MachineRegisterInfo &MRI) {
156   MachineInstr *MI = MRI.getVRegDef(VReg);
157   if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
158     return None;
159 
160   if (MI->getOperand(1).isImm())
161     return MI->getOperand(1).getImm();
162 
163   if (MI->getOperand(1).isCImm() &&
164       MI->getOperand(1).getCImm()->getBitWidth() <= 64)
165     return MI->getOperand(1).getCImm()->getSExtValue();
166 
167   return None;
168 }
169 
170 const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
171                                        const MachineRegisterInfo &MRI) {
172   MachineInstr *MI = MRI.getVRegDef(VReg);
173   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
174     return nullptr;
175   return MI->getOperand(1).getFPImm();
176 }
177 
178 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
179                                        const MachineRegisterInfo &MRI) {
180   auto *DefMI = MRI.getVRegDef(Reg);
181   auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
182   if (!DstTy.isValid())
183     return nullptr;
184   while (DefMI->getOpcode() == TargetOpcode::COPY) {
185     unsigned SrcReg = DefMI->getOperand(1).getReg();
186     auto SrcTy = MRI.getType(SrcReg);
187     if (!SrcTy.isValid() || SrcTy != DstTy)
188       break;
189     DefMI = MRI.getVRegDef(SrcReg);
190   }
191   return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
192 }
193