1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/Utils.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetPassConfig.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 
24 #define DEBUG_TYPE "globalisel-utils"
25 
26 using namespace llvm;
27 
28 unsigned llvm::constrainOperandRegClass(
29     const MachineFunction &MF, const TargetRegisterInfo &TRI,
30     MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
31     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
32     unsigned Reg, unsigned OpIdx) {
33   // Assume physical registers are properly constrained.
34   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
35          "PhysReg not implemented");
36 
37   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
38 
39   if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) {
40     unsigned NewReg = MRI.createVirtualRegister(RegClass);
41     BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
42             TII.get(TargetOpcode::COPY), NewReg)
43         .addReg(Reg);
44     return NewReg;
45   }
46 
47   return Reg;
48 }
49 
50 bool llvm::isTriviallyDead(const MachineInstr &MI,
51                            const MachineRegisterInfo &MRI) {
52   // If we can move an instruction, we can remove it.  Otherwise, it has
53   // a side-effect of some sort.
54   bool SawStore = false;
55   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
56     return false;
57 
58   // Instructions without side-effects are dead iff they only define dead vregs.
59   for (auto &MO : MI.operands()) {
60     if (!MO.isReg() || !MO.isDef())
61       continue;
62 
63     unsigned Reg = MO.getReg();
64     if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
65         !MRI.use_nodbg_empty(Reg))
66       return false;
67   }
68   return true;
69 }
70 
71 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
72                               MachineOptimizationRemarkEmitter &MORE,
73                               MachineOptimizationRemarkMissed &R) {
74   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
75 
76   // Print the function name explicitly if we don't have a debug location (which
77   // makes the diagnostic less useful) or if we're going to emit a raw error.
78   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
79     R << (" (in function: " + MF.getName() + ")").str();
80 
81   if (TPC.isGlobalISelAbortEnabled())
82     report_fatal_error(R.getMsg());
83   else
84     MORE.emit(R);
85 }
86 
87 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
88                               MachineOptimizationRemarkEmitter &MORE,
89                               const char *PassName, StringRef Msg,
90                               const MachineInstr &MI) {
91   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
92                                     MI.getDebugLoc(), MI.getParent());
93   R << Msg << ": " << ore::MNV("Inst", MI);
94   reportGISelFailure(MF, TPC, MORE, R);
95 }
96