1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/Utils.h"
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/IR/Constants.h"
25 
26 #define DEBUG_TYPE "globalisel-utils"
27 
28 using namespace llvm;
29 
30 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
31                                    const TargetInstrInfo &TII,
32                                    const RegisterBankInfo &RBI,
33                                    MachineInstr &InsertPt, unsigned Reg,
34                                    const TargetRegisterClass &RegClass) {
35   if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
36     unsigned NewReg = MRI.createVirtualRegister(&RegClass);
37     BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
38             TII.get(TargetOpcode::COPY), NewReg)
39         .addReg(Reg);
40     return NewReg;
41   }
42 
43   return Reg;
44 }
45 
46 unsigned llvm::constrainOperandRegClass(
47     const MachineFunction &MF, const TargetRegisterInfo &TRI,
48     MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
49     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
50     const MachineOperand &RegMO, unsigned OpIdx) {
51   unsigned Reg = RegMO.getReg();
52   // Assume physical registers are properly constrained.
53   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
54          "PhysReg not implemented");
55 
56   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
57   // Some of the target independent instructions, like COPY, may not impose any
58   // register class constraints on some of their operands: If it's a use, we can
59   // skip constraining as the instruction defining the register would constrain
60   // it.
61   if (!RegClass) {
62     assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
63            "Register class constraint is required unless either the "
64            "instruction is target independent or the operand is a use");
65     // FIXME: Just bailing out like this here could be not enough, unless we
66     // expect the users of this function to do the right thing for PHIs and
67     // COPY:
68     //   v1 = COPY v0
69     //   v2 = COPY v1
70     // v1 here may end up not being constrained at all. Please notice that to
71     // reproduce the issue we likely need a destination pattern of a selection
72     // rule producing such extra copies, not just an input GMIR with them as
73     // every existing target using selectImpl handles copies before calling it
74     // and they never reach this function.
75     return Reg;
76   }
77   return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
78 }
79 
80 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
81                                             const TargetInstrInfo &TII,
82                                             const TargetRegisterInfo &TRI,
83                                             const RegisterBankInfo &RBI) {
84   assert(!isPreISelGenericOpcode(I.getOpcode()) &&
85          "A selected instruction is expected");
86   MachineBasicBlock &MBB = *I.getParent();
87   MachineFunction &MF = *MBB.getParent();
88   MachineRegisterInfo &MRI = MF.getRegInfo();
89 
90   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
91     MachineOperand &MO = I.getOperand(OpI);
92 
93     // There's nothing to be done on non-register operands.
94     if (!MO.isReg())
95       continue;
96 
97     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
98     assert(MO.isReg() && "Unsupported non-reg operand");
99 
100     unsigned Reg = MO.getReg();
101     // Physical registers don't need to be constrained.
102     if (TRI.isPhysicalRegister(Reg))
103       continue;
104 
105     // Register operands with a value of 0 (e.g. predicate operands) don't need
106     // to be constrained.
107     if (Reg == 0)
108       continue;
109 
110     // If the operand is a vreg, we should constrain its regclass, and only
111     // insert COPYs if that's impossible.
112     // constrainOperandRegClass does that for us.
113     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
114                                        MO, OpI));
115 
116     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
117     // done.
118     if (MO.isUse()) {
119       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
120       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
121         I.tieOperands(DefIdx, OpI);
122     }
123   }
124   return true;
125 }
126 
127 bool llvm::isTriviallyDead(const MachineInstr &MI,
128                            const MachineRegisterInfo &MRI) {
129   // If we can move an instruction, we can remove it.  Otherwise, it has
130   // a side-effect of some sort.
131   bool SawStore = false;
132   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
133     return false;
134 
135   // Instructions without side-effects are dead iff they only define dead vregs.
136   for (auto &MO : MI.operands()) {
137     if (!MO.isReg() || !MO.isDef())
138       continue;
139 
140     unsigned Reg = MO.getReg();
141     if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
142         !MRI.use_nodbg_empty(Reg))
143       return false;
144   }
145   return true;
146 }
147 
148 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
149                               MachineOptimizationRemarkEmitter &MORE,
150                               MachineOptimizationRemarkMissed &R) {
151   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
152 
153   // Print the function name explicitly if we don't have a debug location (which
154   // makes the diagnostic less useful) or if we're going to emit a raw error.
155   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
156     R << (" (in function: " + MF.getName() + ")").str();
157 
158   if (TPC.isGlobalISelAbortEnabled())
159     report_fatal_error(R.getMsg());
160   else
161     MORE.emit(R);
162 }
163 
164 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
165                               MachineOptimizationRemarkEmitter &MORE,
166                               const char *PassName, StringRef Msg,
167                               const MachineInstr &MI) {
168   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
169                                     MI.getDebugLoc(), MI.getParent());
170   R << Msg;
171   // Printing MI is expensive;  only do it if expensive remarks are enabled.
172   if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
173     R << ": " << ore::MNV("Inst", MI);
174   reportGISelFailure(MF, TPC, MORE, R);
175 }
176 
177 Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
178                                            const MachineRegisterInfo &MRI) {
179   MachineInstr *MI = MRI.getVRegDef(VReg);
180   if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
181     return None;
182 
183   if (MI->getOperand(1).isImm())
184     return MI->getOperand(1).getImm();
185 
186   if (MI->getOperand(1).isCImm() &&
187       MI->getOperand(1).getCImm()->getBitWidth() <= 64)
188     return MI->getOperand(1).getCImm()->getSExtValue();
189 
190   return None;
191 }
192 
193 const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
194                                        const MachineRegisterInfo &MRI) {
195   MachineInstr *MI = MRI.getVRegDef(VReg);
196   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
197     return nullptr;
198   return MI->getOperand(1).getFPImm();
199 }
200 
201 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
202                                        const MachineRegisterInfo &MRI) {
203   auto *DefMI = MRI.getVRegDef(Reg);
204   auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
205   if (!DstTy.isValid())
206     return nullptr;
207   while (DefMI->getOpcode() == TargetOpcode::COPY) {
208     unsigned SrcReg = DefMI->getOperand(1).getReg();
209     auto SrcTy = MRI.getType(SrcReg);
210     if (!SrcTy.isValid() || SrcTy != DstTy)
211       break;
212     DefMI = MRI.getVRegDef(SrcReg);
213   }
214   return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
215 }
216 
217 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
218   if (Size == 32)
219     return APFloat(float(Val));
220   if (Size == 64)
221     return APFloat(Val);
222   if (Size != 16)
223     llvm_unreachable("Unsupported FPConstant size");
224   bool Ignored;
225   APFloat APF(Val);
226   APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
227   return APF;
228 }
229