1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file This file implements the utility functions used by the GlobalISel 10 /// pipeline. 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/CodeGen/GlobalISel/Utils.h" 14 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 15 #include "llvm/CodeGen/MachineInstr.h" 16 #include "llvm/CodeGen/MachineInstrBuilder.h" 17 #include "llvm/CodeGen/MachineRegisterInfo.h" 18 #include "llvm/Target/TargetInstrInfo.h" 19 #include "llvm/Target/TargetRegisterInfo.h" 20 21 #define DEBUG_TYPE "globalisel-utils" 22 23 using namespace llvm; 24 25 unsigned llvm::constrainOperandRegClass( 26 const MachineFunction &MF, const TargetRegisterInfo &TRI, 27 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 28 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, 29 unsigned Reg, unsigned OpIdx) { 30 // Assume physical registers are properly constrained. 31 assert(TargetRegisterInfo::isVirtualRegister(Reg) && 32 "PhysReg not implemented"); 33 34 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); 35 36 if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) { 37 unsigned NewReg = MRI.createVirtualRegister(RegClass); 38 BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(), 39 TII.get(TargetOpcode::COPY), NewReg) 40 .addReg(Reg); 41 return NewReg; 42 } 43 44 return Reg; 45 } 46