1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/Utils.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetPassConfig.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 
25 #define DEBUG_TYPE "globalisel-utils"
26 
27 using namespace llvm;
28 
29 unsigned llvm::constrainOperandRegClass(
30     const MachineFunction &MF, const TargetRegisterInfo &TRI,
31     MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
32     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
33     unsigned Reg, unsigned OpIdx) {
34   // Assume physical registers are properly constrained.
35   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
36          "PhysReg not implemented");
37 
38   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
39 
40   if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) {
41     unsigned NewReg = MRI.createVirtualRegister(RegClass);
42     BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
43             TII.get(TargetOpcode::COPY), NewReg)
44         .addReg(Reg);
45     return NewReg;
46   }
47 
48   return Reg;
49 }
50 
51 bool llvm::isTriviallyDead(const MachineInstr &MI,
52                            const MachineRegisterInfo &MRI) {
53   // If we can move an instruction, we can remove it.  Otherwise, it has
54   // a side-effect of some sort.
55   bool SawStore = false;
56   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
57     return false;
58 
59   // Instructions without side-effects are dead iff they only define dead vregs.
60   for (auto &MO : MI.operands()) {
61     if (!MO.isReg() || !MO.isDef())
62       continue;
63 
64     unsigned Reg = MO.getReg();
65     if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
66         !MRI.use_nodbg_empty(Reg))
67       return false;
68   }
69   return true;
70 }
71 
72 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
73                               MachineOptimizationRemarkEmitter &MORE,
74                               MachineOptimizationRemarkMissed &R) {
75   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
76 
77   // Print the function name explicitly if we don't have a debug location (which
78   // makes the diagnostic less useful) or if we're going to emit a raw error.
79   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
80     R << (" (in function: " + MF.getName() + ")").str();
81 
82   if (TPC.isGlobalISelAbortEnabled())
83     report_fatal_error(R.getMsg());
84   else
85     MORE.emit(R);
86 }
87 
88 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
89                               MachineOptimizationRemarkEmitter &MORE,
90                               const char *PassName, StringRef Msg,
91                               const MachineInstr &MI) {
92   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
93                                     MI.getDebugLoc(), MI.getParent());
94   R << Msg << ": " << ore::MNV("Inst", MI);
95   reportGISelFailure(MF, TPC, MORE, R);
96 }
97 
98 Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
99                                            const MachineRegisterInfo &MRI) {
100   MachineInstr *MI = MRI.getVRegDef(VReg);
101   if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
102     return None;
103 
104   if (MI->getOperand(1).isImm())
105     return MI->getOperand(1).getImm();
106 
107   if (MI->getOperand(1).isCImm() &&
108       MI->getOperand(1).getCImm()->getBitWidth() <= 64)
109     return MI->getOperand(1).getCImm()->getSExtValue();
110 
111   return None;
112 }
113 
114 const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
115                                        const MachineRegisterInfo &MRI) {
116   MachineInstr *MI = MRI.getVRegDef(VReg);
117   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
118     return nullptr;
119   return MI->getOperand(1).getFPImm();
120 }
121