1 //===- PPC64.cpp ----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "Symbols.h" 10 #include "SyntheticSections.h" 11 #include "Target.h" 12 #include "lld/Common/ErrorHandler.h" 13 #include "llvm/Support/Endian.h" 14 15 using namespace llvm; 16 using namespace llvm::object; 17 using namespace llvm::support::endian; 18 using namespace llvm::ELF; 19 using namespace lld; 20 using namespace lld::elf; 21 22 static uint64_t PPC64TocOffset = 0x8000; 23 static uint64_t DynamicThreadPointerOffset = 0x8000; 24 25 // The instruction encoding of bits 21-30 from the ISA for the Xform and Dform 26 // instructions that can be used as part of the initial exec TLS sequence. 27 enum XFormOpcd { 28 LBZX = 87, 29 LHZX = 279, 30 LWZX = 23, 31 LDX = 21, 32 STBX = 215, 33 STHX = 407, 34 STWX = 151, 35 STDX = 149, 36 ADD = 266, 37 }; 38 39 enum DFormOpcd { 40 LBZ = 34, 41 LBZU = 35, 42 LHZ = 40, 43 LHZU = 41, 44 LHAU = 43, 45 LWZ = 32, 46 LWZU = 33, 47 LFSU = 49, 48 LD = 58, 49 LFDU = 51, 50 STB = 38, 51 STBU = 39, 52 STH = 44, 53 STHU = 45, 54 STW = 36, 55 STWU = 37, 56 STFSU = 53, 57 STFDU = 55, 58 STD = 62, 59 ADDI = 14 60 }; 61 62 uint64_t elf::getPPC64TocBase() { 63 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 64 // TOC starts where the first of these sections starts. We always create a 65 // .got when we see a relocation that uses it, so for us the start is always 66 // the .got. 67 uint64_t TocVA = In.Got->getVA(); 68 69 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 70 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 71 // code (crt1.o) assumes that you can get from the TOC base to the 72 // start of the .toc section with only a single (signed) 16-bit relocation. 73 return TocVA + PPC64TocOffset; 74 } 75 76 unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t StOther) { 77 // The offset is encoded into the 3 most significant bits of the st_other 78 // field, with some special values described in section 3.4.1 of the ABI: 79 // 0 --> Zero offset between the GEP and LEP, and the function does NOT use 80 // the TOC pointer (r2). r2 will hold the same value on returning from 81 // the function as it did on entering the function. 82 // 1 --> Zero offset between the GEP and LEP, and r2 should be treated as a 83 // caller-saved register for all callers. 84 // 2-6 --> The binary logarithm of the offset eg: 85 // 2 --> 2^2 = 4 bytes --> 1 instruction. 86 // 6 --> 2^6 = 64 bytes --> 16 instructions. 87 // 7 --> Reserved. 88 uint8_t GepToLep = (StOther >> 5) & 7; 89 if (GepToLep < 2) 90 return 0; 91 92 // The value encoded in the st_other bits is the 93 // log-base-2(offset). 94 if (GepToLep < 7) 95 return 1 << GepToLep; 96 97 error("reserved value of 7 in the 3 most-significant-bits of st_other"); 98 return 0; 99 } 100 101 bool elf::isPPC64SmallCodeModelTocReloc(RelType Type) { 102 // The only small code model relocations that access the .toc section. 103 return Type == R_PPC64_TOC16 || Type == R_PPC64_TOC16_DS; 104 } 105 106 namespace { 107 class PPC64 final : public TargetInfo { 108 public: 109 PPC64(); 110 int getTlsGdRelaxSkip(RelType Type) const override; 111 uint32_t calcEFlags() const override; 112 RelExpr getRelExpr(RelType Type, const Symbol &S, 113 const uint8_t *Loc) const override; 114 void writePltHeader(uint8_t *Buf) const override; 115 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 116 int32_t Index, unsigned RelOff) const override; 117 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 118 void writeGotHeader(uint8_t *Buf) const override; 119 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 120 uint64_t BranchAddr, const Symbol &S) const override; 121 bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override; 122 RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data, 123 RelExpr Expr) const override; 124 void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override; 125 void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override; 126 void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override; 127 void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override; 128 129 bool adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End, 130 uint8_t StOther) const override; 131 }; 132 } // namespace 133 134 // Relocation masks following the #lo(value), #hi(value), #ha(value), 135 // #higher(value), #highera(value), #highest(value), and #highesta(value) 136 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 137 // document. 138 static uint16_t lo(uint64_t V) { return V; } 139 static uint16_t hi(uint64_t V) { return V >> 16; } 140 static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; } 141 static uint16_t higher(uint64_t V) { return V >> 32; } 142 static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; } 143 static uint16_t highest(uint64_t V) { return V >> 48; } 144 static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; } 145 146 // Extracts the 'PO' field of an instruction encoding. 147 static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); } 148 149 static bool isDQFormInstruction(uint32_t Encoding) { 150 switch (getPrimaryOpCode(Encoding)) { 151 default: 152 return false; 153 case 56: 154 // The only instruction with a primary opcode of 56 is `lq`. 155 return true; 156 case 61: 157 // There are both DS and DQ instruction forms with this primary opcode. 158 // Namely `lxv` and `stxv` are the DQ-forms that use it. 159 // The DS 'XO' bits being set to 01 is restricted to DQ form. 160 return (Encoding & 3) == 0x1; 161 } 162 } 163 164 static bool isInstructionUpdateForm(uint32_t Encoding) { 165 switch (getPrimaryOpCode(Encoding)) { 166 default: 167 return false; 168 case LBZU: 169 case LHAU: 170 case LHZU: 171 case LWZU: 172 case LFSU: 173 case LFDU: 174 case STBU: 175 case STHU: 176 case STWU: 177 case STFSU: 178 case STFDU: 179 return true; 180 // LWA has the same opcode as LD, and the DS bits is what differentiates 181 // between LD/LDU/LWA 182 case LD: 183 case STD: 184 return (Encoding & 3) == 1; 185 } 186 } 187 188 // There are a number of places when we either want to read or write an 189 // instruction when handling a half16 relocation type. On big-endian the buffer 190 // pointer is pointing into the middle of the word we want to extract, and on 191 // little-endian it is pointing to the start of the word. These 2 helpers are to 192 // simplify reading and writing in that context. 193 static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) { 194 write32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0), Instr); 195 } 196 197 static uint32_t readInstrFromHalf16(const uint8_t *Loc) { 198 return read32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0)); 199 } 200 201 PPC64::PPC64() { 202 GotRel = R_PPC64_GLOB_DAT; 203 NoneRel = R_PPC64_NONE; 204 PltRel = R_PPC64_JMP_SLOT; 205 RelativeRel = R_PPC64_RELATIVE; 206 IRelativeRel = R_PPC64_IRELATIVE; 207 GotEntrySize = 8; 208 PltEntrySize = 4; 209 GotPltEntrySize = 8; 210 GotBaseSymInGotPlt = false; 211 GotHeaderEntriesNum = 1; 212 GotPltHeaderEntriesNum = 2; 213 PltHeaderSize = 60; 214 NeedsThunks = true; 215 216 TlsModuleIndexRel = R_PPC64_DTPMOD64; 217 TlsOffsetRel = R_PPC64_DTPREL64; 218 219 TlsGotRel = R_PPC64_TPREL64; 220 221 NeedsMoreStackNonSplit = false; 222 223 // We need 64K pages (at least under glibc/Linux, the loader won't 224 // set different permissions on a finer granularity than that). 225 DefaultMaxPageSize = 65536; 226 227 // The PPC64 ELF ABI v1 spec, says: 228 // 229 // It is normally desirable to put segments with different characteristics 230 // in separate 256 Mbyte portions of the address space, to give the 231 // operating system full paging flexibility in the 64-bit address space. 232 // 233 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 234 // use 0x10000000 as the starting address. 235 DefaultImageBase = 0x10000000; 236 237 write32(TrapInstr.data(), 0x7fe00008); 238 } 239 240 int PPC64::getTlsGdRelaxSkip(RelType Type) const { 241 // A __tls_get_addr call instruction is marked with 2 relocations: 242 // 243 // R_PPC64_TLSGD / R_PPC64_TLSLD: marker relocation 244 // R_PPC64_REL24: __tls_get_addr 245 // 246 // After the relaxation we no longer call __tls_get_addr and should skip both 247 // relocations to not create a false dependence on __tls_get_addr being 248 // defined. 249 if (Type == R_PPC64_TLSGD || Type == R_PPC64_TLSLD) 250 return 2; 251 return 1; 252 } 253 254 static uint32_t getEFlags(InputFile *File) { 255 if (Config->EKind == ELF64BEKind) 256 return cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags; 257 return cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags; 258 } 259 260 // This file implements v2 ABI. This function makes sure that all 261 // object files have v2 or an unspecified version as an ABI version. 262 uint32_t PPC64::calcEFlags() const { 263 for (InputFile *F : ObjectFiles) { 264 uint32_t Flag = getEFlags(F); 265 if (Flag == 1) 266 error(toString(F) + ": ABI version 1 is not supported"); 267 else if (Flag > 2) 268 error(toString(F) + ": unrecognized e_flags: " + Twine(Flag)); 269 } 270 return 2; 271 } 272 273 void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const { 274 // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement. 275 // The general dynamic code sequence for a global `x` will look like: 276 // Instruction Relocation Symbol 277 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 278 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 279 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 280 // R_PPC64_REL24 __tls_get_addr 281 // nop None None 282 283 // Relaxing to local exec entails converting: 284 // addis r3, r2, x@got@tlsgd@ha into nop 285 // addi r3, r3, x@got@tlsgd@l into addis r3, r13, x@tprel@ha 286 // bl __tls_get_addr(x@tlsgd) into nop 287 // nop into addi r3, r3, x@tprel@l 288 289 switch (Type) { 290 case R_PPC64_GOT_TLSGD16_HA: 291 writeInstrFromHalf16(Loc, 0x60000000); // nop 292 break; 293 case R_PPC64_GOT_TLSGD16: 294 case R_PPC64_GOT_TLSGD16_LO: 295 writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13 296 relocateOne(Loc, R_PPC64_TPREL16_HA, Val); 297 break; 298 case R_PPC64_TLSGD: 299 write32(Loc, 0x60000000); // nop 300 write32(Loc + 4, 0x38630000); // addi r3, r3 301 // Since we are relocating a half16 type relocation and Loc + 4 points to 302 // the start of an instruction we need to advance the buffer by an extra 303 // 2 bytes on BE. 304 relocateOne(Loc + 4 + (Config->EKind == ELF64BEKind ? 2 : 0), 305 R_PPC64_TPREL16_LO, Val); 306 break; 307 default: 308 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 309 } 310 } 311 312 void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const { 313 // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement. 314 // The local dynamic code sequence for a global `x` will look like: 315 // Instruction Relocation Symbol 316 // addis r3, r2, x@got@tlsld@ha R_PPC64_GOT_TLSLD16_HA x 317 // addi r3, r3, x@got@tlsld@l R_PPC64_GOT_TLSLD16_LO x 318 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSLD x 319 // R_PPC64_REL24 __tls_get_addr 320 // nop None None 321 322 // Relaxing to local exec entails converting: 323 // addis r3, r2, x@got@tlsld@ha into nop 324 // addi r3, r3, x@got@tlsld@l into addis r3, r13, 0 325 // bl __tls_get_addr(x@tlsgd) into nop 326 // nop into addi r3, r3, 4096 327 328 switch (Type) { 329 case R_PPC64_GOT_TLSLD16_HA: 330 writeInstrFromHalf16(Loc, 0x60000000); // nop 331 break; 332 case R_PPC64_GOT_TLSLD16_LO: 333 writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0 334 break; 335 case R_PPC64_TLSLD: 336 write32(Loc, 0x60000000); // nop 337 write32(Loc + 4, 0x38631000); // addi r3, r3, 4096 338 break; 339 case R_PPC64_DTPREL16: 340 case R_PPC64_DTPREL16_HA: 341 case R_PPC64_DTPREL16_HI: 342 case R_PPC64_DTPREL16_DS: 343 case R_PPC64_DTPREL16_LO: 344 case R_PPC64_DTPREL16_LO_DS: 345 case R_PPC64_GOT_DTPREL16_HA: 346 case R_PPC64_GOT_DTPREL16_LO_DS: 347 case R_PPC64_GOT_DTPREL16_DS: 348 case R_PPC64_GOT_DTPREL16_HI: 349 relocateOne(Loc, Type, Val); 350 break; 351 default: 352 llvm_unreachable("unsupported relocation for TLS LD to LE relaxation"); 353 } 354 } 355 356 static unsigned getDFormOp(unsigned SecondaryOp) { 357 switch (SecondaryOp) { 358 case LBZX: 359 return LBZ; 360 case LHZX: 361 return LHZ; 362 case LWZX: 363 return LWZ; 364 case LDX: 365 return LD; 366 case STBX: 367 return STB; 368 case STHX: 369 return STH; 370 case STWX: 371 return STW; 372 case STDX: 373 return STD; 374 case ADD: 375 return ADDI; 376 default: 377 error("unrecognized instruction for IE to LE R_PPC64_TLS"); 378 return 0; 379 } 380 } 381 382 void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const { 383 // The initial exec code sequence for a global `x` will look like: 384 // Instruction Relocation Symbol 385 // addis r9, r2, x@got@tprel@ha R_PPC64_GOT_TPREL16_HA x 386 // ld r9, x@got@tprel@l(r9) R_PPC64_GOT_TPREL16_LO_DS x 387 // add r9, r9, x@tls R_PPC64_TLS x 388 389 // Relaxing to local exec entails converting: 390 // addis r9, r2, x@got@tprel@ha into nop 391 // ld r9, x@got@tprel@l(r9) into addis r9, r13, x@tprel@ha 392 // add r9, r9, x@tls into addi r9, r9, x@tprel@l 393 394 // x@tls R_PPC64_TLS is a relocation which does not compute anything, 395 // it is replaced with r13 (thread pointer). 396 397 // The add instruction in the initial exec sequence has multiple variations 398 // that need to be handled. If we are building an address it will use an add 399 // instruction, if we are accessing memory it will use any of the X-form 400 // indexed load or store instructions. 401 402 unsigned Offset = (Config->EKind == ELF64BEKind) ? 2 : 0; 403 switch (Type) { 404 case R_PPC64_GOT_TPREL16_HA: 405 write32(Loc - Offset, 0x60000000); // nop 406 break; 407 case R_PPC64_GOT_TPREL16_LO_DS: 408 case R_PPC64_GOT_TPREL16_DS: { 409 uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10 410 write32(Loc - Offset, 0x3C0D0000 | RegNo); // addis RegNo, r13 411 relocateOne(Loc, R_PPC64_TPREL16_HA, Val); 412 break; 413 } 414 case R_PPC64_TLS: { 415 uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc)); 416 if (PrimaryOp != 31) 417 error("unrecognized instruction for IE to LE R_PPC64_TLS"); 418 uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30 419 uint32_t DFormOp = getDFormOp(SecondaryOp); 420 write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF))); 421 relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val); 422 break; 423 } 424 default: 425 llvm_unreachable("unknown relocation for IE to LE"); 426 break; 427 } 428 } 429 430 RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S, 431 const uint8_t *Loc) const { 432 switch (Type) { 433 case R_PPC64_GOT16: 434 case R_PPC64_GOT16_DS: 435 case R_PPC64_GOT16_HA: 436 case R_PPC64_GOT16_HI: 437 case R_PPC64_GOT16_LO: 438 case R_PPC64_GOT16_LO_DS: 439 return R_GOT_OFF; 440 case R_PPC64_TOC16: 441 case R_PPC64_TOC16_DS: 442 case R_PPC64_TOC16_HA: 443 case R_PPC64_TOC16_HI: 444 case R_PPC64_TOC16_LO: 445 case R_PPC64_TOC16_LO_DS: 446 return R_GOTREL; 447 case R_PPC64_TOC: 448 return R_PPC_TOC; 449 case R_PPC64_REL14: 450 case R_PPC64_REL24: 451 return R_PPC_CALL_PLT; 452 case R_PPC64_REL16_LO: 453 case R_PPC64_REL16_HA: 454 case R_PPC64_REL32: 455 case R_PPC64_REL64: 456 return R_PC; 457 case R_PPC64_GOT_TLSGD16: 458 case R_PPC64_GOT_TLSGD16_HA: 459 case R_PPC64_GOT_TLSGD16_HI: 460 case R_PPC64_GOT_TLSGD16_LO: 461 return R_TLSGD_GOT; 462 case R_PPC64_GOT_TLSLD16: 463 case R_PPC64_GOT_TLSLD16_HA: 464 case R_PPC64_GOT_TLSLD16_HI: 465 case R_PPC64_GOT_TLSLD16_LO: 466 return R_TLSLD_GOT; 467 case R_PPC64_GOT_TPREL16_HA: 468 case R_PPC64_GOT_TPREL16_LO_DS: 469 case R_PPC64_GOT_TPREL16_DS: 470 case R_PPC64_GOT_TPREL16_HI: 471 return R_GOT_OFF; 472 case R_PPC64_GOT_DTPREL16_HA: 473 case R_PPC64_GOT_DTPREL16_LO_DS: 474 case R_PPC64_GOT_DTPREL16_DS: 475 case R_PPC64_GOT_DTPREL16_HI: 476 return R_TLSLD_GOT_OFF; 477 case R_PPC64_TPREL16: 478 case R_PPC64_TPREL16_HA: 479 case R_PPC64_TPREL16_LO: 480 case R_PPC64_TPREL16_HI: 481 case R_PPC64_TPREL16_DS: 482 case R_PPC64_TPREL16_LO_DS: 483 case R_PPC64_TPREL16_HIGHER: 484 case R_PPC64_TPREL16_HIGHERA: 485 case R_PPC64_TPREL16_HIGHEST: 486 case R_PPC64_TPREL16_HIGHESTA: 487 return R_TLS; 488 case R_PPC64_DTPREL16: 489 case R_PPC64_DTPREL16_DS: 490 case R_PPC64_DTPREL16_HA: 491 case R_PPC64_DTPREL16_HI: 492 case R_PPC64_DTPREL16_HIGHER: 493 case R_PPC64_DTPREL16_HIGHERA: 494 case R_PPC64_DTPREL16_HIGHEST: 495 case R_PPC64_DTPREL16_HIGHESTA: 496 case R_PPC64_DTPREL16_LO: 497 case R_PPC64_DTPREL16_LO_DS: 498 case R_PPC64_DTPREL64: 499 return R_DTPREL; 500 case R_PPC64_TLSGD: 501 return R_TLSDESC_CALL; 502 case R_PPC64_TLSLD: 503 return R_TLSLD_HINT; 504 case R_PPC64_TLS: 505 return R_TLSIE_HINT; 506 default: 507 return R_ABS; 508 } 509 } 510 511 void PPC64::writeGotHeader(uint8_t *Buf) const { 512 write64(Buf, getPPC64TocBase()); 513 } 514 515 void PPC64::writePltHeader(uint8_t *Buf) const { 516 // The generic resolver stub goes first. 517 write32(Buf + 0, 0x7c0802a6); // mflr r0 518 write32(Buf + 4, 0x429f0005); // bcl 20,4*cr7+so,8 <_glink+0x8> 519 write32(Buf + 8, 0x7d6802a6); // mflr r11 520 write32(Buf + 12, 0x7c0803a6); // mtlr r0 521 write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12 522 write32(Buf + 20, 0x380cffcc); // subi r0,r12,52 523 write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2 524 write32(Buf + 28, 0xe98b002c); // ld r12,44(r11) 525 write32(Buf + 32, 0x7d6c5a14); // add r11,r12,r11 526 write32(Buf + 36, 0xe98b0000); // ld r12,0(r11) 527 write32(Buf + 40, 0xe96b0008); // ld r11,8(r11) 528 write32(Buf + 44, 0x7d8903a6); // mtctr r12 529 write32(Buf + 48, 0x4e800420); // bctr 530 531 // The 'bcl' instruction will set the link register to the address of the 532 // following instruction ('mflr r11'). Here we store the offset from that 533 // instruction to the first entry in the GotPlt section. 534 int64_t GotPltOffset = In.GotPlt->getVA() - (In.Plt->getVA() + 8); 535 write64(Buf + 52, GotPltOffset); 536 } 537 538 void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 539 uint64_t PltEntryAddr, int32_t Index, 540 unsigned RelOff) const { 541 int32_t Offset = PltHeaderSize + Index * PltEntrySize; 542 // bl __glink_PLTresolve 543 write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc)); 544 } 545 546 static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) { 547 // Relocations relative to the toc-base need to be adjusted by the Toc offset. 548 uint64_t TocBiasedVal = Val - PPC64TocOffset; 549 // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset. 550 uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset; 551 552 switch (Type) { 553 // TOC biased relocation. 554 case R_PPC64_GOT16: 555 case R_PPC64_GOT_TLSGD16: 556 case R_PPC64_GOT_TLSLD16: 557 case R_PPC64_TOC16: 558 return {R_PPC64_ADDR16, TocBiasedVal}; 559 case R_PPC64_GOT16_DS: 560 case R_PPC64_TOC16_DS: 561 case R_PPC64_GOT_TPREL16_DS: 562 case R_PPC64_GOT_DTPREL16_DS: 563 return {R_PPC64_ADDR16_DS, TocBiasedVal}; 564 case R_PPC64_GOT16_HA: 565 case R_PPC64_GOT_TLSGD16_HA: 566 case R_PPC64_GOT_TLSLD16_HA: 567 case R_PPC64_GOT_TPREL16_HA: 568 case R_PPC64_GOT_DTPREL16_HA: 569 case R_PPC64_TOC16_HA: 570 return {R_PPC64_ADDR16_HA, TocBiasedVal}; 571 case R_PPC64_GOT16_HI: 572 case R_PPC64_GOT_TLSGD16_HI: 573 case R_PPC64_GOT_TLSLD16_HI: 574 case R_PPC64_GOT_TPREL16_HI: 575 case R_PPC64_GOT_DTPREL16_HI: 576 case R_PPC64_TOC16_HI: 577 return {R_PPC64_ADDR16_HI, TocBiasedVal}; 578 case R_PPC64_GOT16_LO: 579 case R_PPC64_GOT_TLSGD16_LO: 580 case R_PPC64_GOT_TLSLD16_LO: 581 case R_PPC64_TOC16_LO: 582 return {R_PPC64_ADDR16_LO, TocBiasedVal}; 583 case R_PPC64_GOT16_LO_DS: 584 case R_PPC64_TOC16_LO_DS: 585 case R_PPC64_GOT_TPREL16_LO_DS: 586 case R_PPC64_GOT_DTPREL16_LO_DS: 587 return {R_PPC64_ADDR16_LO_DS, TocBiasedVal}; 588 589 // Dynamic Thread pointer biased relocation types. 590 case R_PPC64_DTPREL16: 591 return {R_PPC64_ADDR16, DTPBiasedVal}; 592 case R_PPC64_DTPREL16_DS: 593 return {R_PPC64_ADDR16_DS, DTPBiasedVal}; 594 case R_PPC64_DTPREL16_HA: 595 return {R_PPC64_ADDR16_HA, DTPBiasedVal}; 596 case R_PPC64_DTPREL16_HI: 597 return {R_PPC64_ADDR16_HI, DTPBiasedVal}; 598 case R_PPC64_DTPREL16_HIGHER: 599 return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal}; 600 case R_PPC64_DTPREL16_HIGHERA: 601 return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal}; 602 case R_PPC64_DTPREL16_HIGHEST: 603 return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal}; 604 case R_PPC64_DTPREL16_HIGHESTA: 605 return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal}; 606 case R_PPC64_DTPREL16_LO: 607 return {R_PPC64_ADDR16_LO, DTPBiasedVal}; 608 case R_PPC64_DTPREL16_LO_DS: 609 return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal}; 610 case R_PPC64_DTPREL64: 611 return {R_PPC64_ADDR64, DTPBiasedVal}; 612 613 default: 614 return {Type, Val}; 615 } 616 } 617 618 static bool isTocOptType(RelType Type) { 619 switch (Type) { 620 case R_PPC64_GOT16_HA: 621 case R_PPC64_GOT16_LO_DS: 622 case R_PPC64_TOC16_HA: 623 case R_PPC64_TOC16_LO_DS: 624 case R_PPC64_TOC16_LO: 625 return true; 626 default: 627 return false; 628 } 629 } 630 631 void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 632 // We need to save the original relocation type to use in diagnostics, and 633 // use the original type to determine if we should toc-optimize the 634 // instructions being relocated. 635 RelType OriginalType = Type; 636 bool ShouldTocOptimize = isTocOptType(Type); 637 // For dynamic thread pointer relative, toc-relative, and got-indirect 638 // relocations, proceed in terms of the corresponding ADDR16 relocation type. 639 std::tie(Type, Val) = toAddr16Rel(Type, Val); 640 641 switch (Type) { 642 case R_PPC64_ADDR14: { 643 checkAlignment(Loc, Val, 4, Type); 644 // Preserve the AA/LK bits in the branch instruction 645 uint8_t AALK = Loc[3]; 646 write16(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 647 break; 648 } 649 case R_PPC64_ADDR16: 650 case R_PPC64_TPREL16: 651 checkInt(Loc, Val, 16, OriginalType); 652 write16(Loc, Val); 653 break; 654 case R_PPC64_ADDR16_DS: 655 case R_PPC64_TPREL16_DS: { 656 checkInt(Loc, Val, 16, OriginalType); 657 // DQ-form instructions use bits 28-31 as part of the instruction encoding 658 // DS-form instructions only use bits 30-31. 659 uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 0xF : 0x3; 660 checkAlignment(Loc, lo(Val), Mask + 1, OriginalType); 661 write16(Loc, (read16(Loc) & Mask) | lo(Val)); 662 } break; 663 case R_PPC64_ADDR16_HA: 664 case R_PPC64_REL16_HA: 665 case R_PPC64_TPREL16_HA: 666 if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) 667 writeInstrFromHalf16(Loc, 0x60000000); 668 else 669 write16(Loc, ha(Val)); 670 break; 671 case R_PPC64_ADDR16_HI: 672 case R_PPC64_REL16_HI: 673 case R_PPC64_TPREL16_HI: 674 write16(Loc, hi(Val)); 675 break; 676 case R_PPC64_ADDR16_HIGHER: 677 case R_PPC64_TPREL16_HIGHER: 678 write16(Loc, higher(Val)); 679 break; 680 case R_PPC64_ADDR16_HIGHERA: 681 case R_PPC64_TPREL16_HIGHERA: 682 write16(Loc, highera(Val)); 683 break; 684 case R_PPC64_ADDR16_HIGHEST: 685 case R_PPC64_TPREL16_HIGHEST: 686 write16(Loc, highest(Val)); 687 break; 688 case R_PPC64_ADDR16_HIGHESTA: 689 case R_PPC64_TPREL16_HIGHESTA: 690 write16(Loc, highesta(Val)); 691 break; 692 case R_PPC64_ADDR16_LO: 693 case R_PPC64_REL16_LO: 694 case R_PPC64_TPREL16_LO: 695 // When the high-adjusted part of a toc relocation evalutes to 0, it is 696 // changed into a nop. The lo part then needs to be updated to use the 697 // toc-pointer register r2, as the base register. 698 if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) { 699 uint32_t Instr = readInstrFromHalf16(Loc); 700 if (isInstructionUpdateForm(Instr)) 701 error(getErrorLocation(Loc) + 702 "can't toc-optimize an update instruction: 0x" + 703 utohexstr(Instr)); 704 Instr = (Instr & 0xFFE00000) | 0x00020000; 705 writeInstrFromHalf16(Loc, Instr); 706 } 707 write16(Loc, lo(Val)); 708 break; 709 case R_PPC64_ADDR16_LO_DS: 710 case R_PPC64_TPREL16_LO_DS: { 711 // DQ-form instructions use bits 28-31 as part of the instruction encoding 712 // DS-form instructions only use bits 30-31. 713 uint32_t Inst = readInstrFromHalf16(Loc); 714 uint16_t Mask = isDQFormInstruction(Inst) ? 0xF : 0x3; 715 checkAlignment(Loc, lo(Val), Mask + 1, OriginalType); 716 if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) { 717 // When the high-adjusted part of a toc relocation evalutes to 0, it is 718 // changed into a nop. The lo part then needs to be updated to use the toc 719 // pointer register r2, as the base register. 720 if (isInstructionUpdateForm(Inst)) 721 error(getErrorLocation(Loc) + 722 "Can't toc-optimize an update instruction: 0x" + 723 Twine::utohexstr(Inst)); 724 Inst = (Inst & 0xFFE0000F) | 0x00020000; 725 writeInstrFromHalf16(Loc, Inst); 726 } 727 write16(Loc, (read16(Loc) & Mask) | lo(Val)); 728 } break; 729 case R_PPC64_ADDR32: 730 case R_PPC64_REL32: 731 checkInt(Loc, Val, 32, Type); 732 write32(Loc, Val); 733 break; 734 case R_PPC64_ADDR64: 735 case R_PPC64_REL64: 736 case R_PPC64_TOC: 737 write64(Loc, Val); 738 break; 739 case R_PPC64_REL14: { 740 uint32_t Mask = 0x0000FFFC; 741 checkInt(Loc, Val, 16, Type); 742 checkAlignment(Loc, Val, 4, Type); 743 write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask)); 744 break; 745 } 746 case R_PPC64_REL24: { 747 uint32_t Mask = 0x03FFFFFC; 748 checkInt(Loc, Val, 26, Type); 749 checkAlignment(Loc, Val, 4, Type); 750 write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask)); 751 break; 752 } 753 case R_PPC64_DTPREL64: 754 write64(Loc, Val - DynamicThreadPointerOffset); 755 break; 756 default: 757 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 758 } 759 } 760 761 bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 762 uint64_t BranchAddr, const Symbol &S) const { 763 if (Type != R_PPC64_REL14 && Type != R_PPC64_REL24) 764 return false; 765 766 // If a function is in the Plt it needs to be called with a call-stub. 767 if (S.isInPlt()) 768 return true; 769 770 // If a symbol is a weak undefined and we are compiling an executable 771 // it doesn't need a range-extending thunk since it can't be called. 772 if (S.isUndefWeak() && !Config->Shared) 773 return false; 774 775 // If the offset exceeds the range of the branch type then it will need 776 // a range-extending thunk. 777 // See the comment in getRelocTargetVA() about R_PPC64_CALL. 778 return !inBranchRange(Type, BranchAddr, 779 S.getVA() + 780 getPPC64GlobalEntryToLocalEntryOffset(S.StOther)); 781 } 782 783 bool PPC64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const { 784 int64_t Offset = Dst - Src; 785 if (Type == R_PPC64_REL14) 786 return isInt<16>(Offset); 787 if (Type == R_PPC64_REL24) 788 return isInt<26>(Offset); 789 llvm_unreachable("unsupported relocation type used in branch"); 790 } 791 792 RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data, 793 RelExpr Expr) const { 794 if (Expr == R_RELAX_TLS_GD_TO_IE) 795 return R_RELAX_TLS_GD_TO_IE_GOT_OFF; 796 if (Expr == R_RELAX_TLS_LD_TO_LE) 797 return R_RELAX_TLS_LD_TO_LE_ABS; 798 return Expr; 799 } 800 801 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement. 802 // The general dynamic code sequence for a global `x` uses 4 instructions. 803 // Instruction Relocation Symbol 804 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 805 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 806 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 807 // R_PPC64_REL24 __tls_get_addr 808 // nop None None 809 // 810 // Relaxing to initial-exec entails: 811 // 1) Convert the addis/addi pair that builds the address of the tls_index 812 // struct for 'x' to an addis/ld pair that loads an offset from a got-entry. 813 // 2) Convert the call to __tls_get_addr to a nop. 814 // 3) Convert the nop following the call to an add of the loaded offset to the 815 // thread pointer. 816 // Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is 817 // used as the relaxation hint for both steps 2 and 3. 818 void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const { 819 switch (Type) { 820 case R_PPC64_GOT_TLSGD16_HA: 821 // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to 822 // addis rT, r2, sym@got@tprel@ha. 823 relocateOne(Loc, R_PPC64_GOT_TPREL16_HA, Val); 824 return; 825 case R_PPC64_GOT_TLSGD16_LO: { 826 // Relax from addi r3, rA, sym@got@tlsgd@l to 827 // ld r3, sym@got@tprel@l(rA) 828 uint32_t InputRegister = (readInstrFromHalf16(Loc) & (0x1f << 16)); 829 writeInstrFromHalf16(Loc, 0xE8600000 | InputRegister); 830 relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val); 831 return; 832 } 833 case R_PPC64_TLSGD: 834 write32(Loc, 0x60000000); // bl __tls_get_addr(sym@tlsgd) --> nop 835 write32(Loc + 4, 0x7c636A14); // nop --> add r3, r3, r13 836 return; 837 default: 838 llvm_unreachable("unsupported relocation for TLS GD to IE relaxation"); 839 } 840 } 841 842 // The prologue for a split-stack function is expected to look roughly 843 // like this: 844 // .Lglobal_entry_point: 845 // # TOC pointer initalization. 846 // ... 847 // .Llocal_entry_point: 848 // # load the __private_ss member of the threads tcbhead. 849 // ld r0,-0x7000-64(r13) 850 // # subtract the functions stack size from the stack pointer. 851 // addis r12, r1, ha(-stack-frame size) 852 // addi r12, r12, l(-stack-frame size) 853 // # compare needed to actual and branch to allocate_more_stack if more 854 // # space is needed, otherwise fallthrough to 'normal' function body. 855 // cmpld cr7,r12,r0 856 // blt- cr7, .Lallocate_more_stack 857 // 858 // -) The allocate_more_stack block might be placed after the split-stack 859 // prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body` 860 // instead. 861 // -) If either the addis or addi is not needed due to the stack size being 862 // smaller then 32K or a multiple of 64K they will be replaced with a nop, 863 // but there will always be 2 instructions the linker can overwrite for the 864 // adjusted stack size. 865 // 866 // The linkers job here is to increase the stack size used in the addis/addi 867 // pair by split-stack-size-adjust. 868 // addis r12, r1, ha(-stack-frame size - split-stack-adjust-size) 869 // addi r12, r12, l(-stack-frame size - split-stack-adjust-size) 870 bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End, 871 uint8_t StOther) const { 872 // If the caller has a global entry point adjust the buffer past it. The start 873 // of the split-stack prologue will be at the local entry point. 874 Loc += getPPC64GlobalEntryToLocalEntryOffset(StOther); 875 876 // At the very least we expect to see a load of some split-stack data from the 877 // tcb, and 2 instructions that calculate the ending stack address this 878 // function will require. If there is not enough room for at least 3 879 // instructions it can't be a split-stack prologue. 880 if (Loc + 12 >= End) 881 return false; 882 883 // First instruction must be `ld r0, -0x7000-64(r13)` 884 if (read32(Loc) != 0xe80d8fc0) 885 return false; 886 887 int16_t HiImm = 0; 888 int16_t LoImm = 0; 889 // First instruction can be either an addis if the frame size is larger then 890 // 32K, or an addi if the size is less then 32K. 891 int32_t FirstInstr = read32(Loc + 4); 892 if (getPrimaryOpCode(FirstInstr) == 15) { 893 HiImm = FirstInstr & 0xFFFF; 894 } else if (getPrimaryOpCode(FirstInstr) == 14) { 895 LoImm = FirstInstr & 0xFFFF; 896 } else { 897 return false; 898 } 899 900 // Second instruction is either an addi or a nop. If the first instruction was 901 // an addi then LoImm is set and the second instruction must be a nop. 902 uint32_t SecondInstr = read32(Loc + 8); 903 if (!LoImm && getPrimaryOpCode(SecondInstr) == 14) { 904 LoImm = SecondInstr & 0xFFFF; 905 } else if (SecondInstr != 0x60000000) { 906 return false; 907 } 908 909 // The register operands of the first instruction should be the stack-pointer 910 // (r1) as the input (RA) and r12 as the output (RT). If the second 911 // instruction is not a nop, then it should use r12 as both input and output. 912 auto CheckRegOperands = [](uint32_t Instr, uint8_t ExpectedRT, 913 uint8_t ExpectedRA) { 914 return ((Instr & 0x3E00000) >> 21 == ExpectedRT) && 915 ((Instr & 0x1F0000) >> 16 == ExpectedRA); 916 }; 917 if (!CheckRegOperands(FirstInstr, 12, 1)) 918 return false; 919 if (SecondInstr != 0x60000000 && !CheckRegOperands(SecondInstr, 12, 12)) 920 return false; 921 922 int32_t StackFrameSize = (HiImm * 65536) + LoImm; 923 // Check that the adjusted size doesn't overflow what we can represent with 2 924 // instructions. 925 if (StackFrameSize < Config->SplitStackAdjustSize + INT32_MIN) { 926 error(getErrorLocation(Loc) + "split-stack prologue adjustment overflows"); 927 return false; 928 } 929 930 int32_t AdjustedStackFrameSize = 931 StackFrameSize - Config->SplitStackAdjustSize; 932 933 LoImm = AdjustedStackFrameSize & 0xFFFF; 934 HiImm = (AdjustedStackFrameSize + 0x8000) >> 16; 935 if (HiImm) { 936 write32(Loc + 4, 0x3D810000 | (uint16_t)HiImm); 937 // If the low immediate is zero the second instruction will be a nop. 938 SecondInstr = LoImm ? 0x398C0000 | (uint16_t)LoImm : 0x60000000; 939 write32(Loc + 8, SecondInstr); 940 } else { 941 // addi r12, r1, imm 942 write32(Loc + 4, (0x39810000) | (uint16_t)LoImm); 943 write32(Loc + 8, 0x60000000); 944 } 945 946 return true; 947 } 948 949 TargetInfo *elf::getPPC64TargetInfo() { 950 static PPC64 Target; 951 return &Target; 952 } 953