1 //===- PPC64.cpp ----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "lld/Common/ErrorHandler.h" 14 #include "llvm/Support/Endian.h" 15 16 using namespace llvm; 17 using namespace llvm::object; 18 using namespace llvm::support::endian; 19 using namespace llvm::ELF; 20 using namespace lld; 21 using namespace lld::elf; 22 23 static uint64_t PPC64TocOffset = 0x8000; 24 static uint64_t DynamicThreadPointerOffset = 0x8000; 25 26 uint64_t elf::getPPC64TocBase() { 27 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 28 // TOC starts where the first of these sections starts. We always create a 29 // .got when we see a relocation that uses it, so for us the start is always 30 // the .got. 31 uint64_t TocVA = InX::Got->getVA(); 32 33 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 34 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 35 // code (crt1.o) assumes that you can get from the TOC base to the 36 // start of the .toc section with only a single (signed) 16-bit relocation. 37 return TocVA + PPC64TocOffset; 38 } 39 40 namespace { 41 class PPC64 final : public TargetInfo { 42 public: 43 PPC64(); 44 uint32_t calcEFlags() const override; 45 RelExpr getRelExpr(RelType Type, const Symbol &S, 46 const uint8_t *Loc) const override; 47 void writePltHeader(uint8_t *Buf) const override; 48 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 49 int32_t Index, unsigned RelOff) const override; 50 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 51 void writeGotHeader(uint8_t *Buf) const override; 52 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 53 uint64_t BranchAddr, const Symbol &S) const override; 54 RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data, 55 RelExpr Expr) const override; 56 void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override; 57 void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override; 58 }; 59 } // namespace 60 61 // Relocation masks following the #lo(value), #hi(value), #ha(value), 62 // #higher(value), #highera(value), #highest(value), and #highesta(value) 63 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 64 // document. 65 static uint16_t lo(uint64_t V) { return V; } 66 static uint16_t hi(uint64_t V) { return V >> 16; } 67 static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; } 68 static uint16_t higher(uint64_t V) { return V >> 32; } 69 static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; } 70 static uint16_t highest(uint64_t V) { return V >> 48; } 71 static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; } 72 73 PPC64::PPC64() { 74 GotRel = R_PPC64_GLOB_DAT; 75 PltRel = R_PPC64_JMP_SLOT; 76 RelativeRel = R_PPC64_RELATIVE; 77 IRelativeRel = R_PPC64_IRELATIVE; 78 GotEntrySize = 8; 79 PltEntrySize = 4; 80 GotPltEntrySize = 8; 81 GotBaseSymInGotPlt = false; 82 GotBaseSymOff = 0x8000; 83 GotHeaderEntriesNum = 1; 84 GotPltHeaderEntriesNum = 2; 85 PltHeaderSize = 60; 86 NeedsThunks = true; 87 TcbSize = 8; 88 TlsTpOffset = 0x7000; 89 90 TlsModuleIndexRel = R_PPC64_DTPMOD64; 91 TlsOffsetRel = R_PPC64_DTPREL64; 92 93 TlsGotRel = R_PPC64_TPREL64; 94 95 // We need 64K pages (at least under glibc/Linux, the loader won't 96 // set different permissions on a finer granularity than that). 97 DefaultMaxPageSize = 65536; 98 99 // The PPC64 ELF ABI v1 spec, says: 100 // 101 // It is normally desirable to put segments with different characteristics 102 // in separate 256 Mbyte portions of the address space, to give the 103 // operating system full paging flexibility in the 64-bit address space. 104 // 105 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 106 // use 0x10000000 as the starting address. 107 DefaultImageBase = 0x10000000; 108 109 TrapInstr = 110 (Config->IsLE == sys::IsLittleEndianHost) ? 0x7fe00008 : 0x0800e07f; 111 } 112 113 static uint32_t getEFlags(InputFile *File) { 114 // Get the e_flag from the input file and issue an error if incompatible 115 // e_flag encountered. 116 uint32_t EFlags; 117 switch (Config->EKind) { 118 case ELF64BEKind: 119 EFlags = cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags; 120 break; 121 case ELF64LEKind: 122 EFlags = cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags; 123 break; 124 default: 125 llvm_unreachable("unknown Config->EKind"); 126 } 127 if (EFlags > 2) { 128 error("incompatible e_flags: " + toString(File)); 129 return 0; 130 } 131 return EFlags; 132 } 133 134 uint32_t PPC64::calcEFlags() const { 135 assert(!ObjectFiles.empty()); 136 137 uint32_t NonZeroFlag; 138 for (InputFile *F : makeArrayRef(ObjectFiles)) { 139 NonZeroFlag = getEFlags(F); 140 if (NonZeroFlag) 141 break; 142 } 143 144 // Verify that all input files have either the same e_flags, or zero. 145 for (InputFile *F : makeArrayRef(ObjectFiles)) { 146 uint32_t Flag = getEFlags(F); 147 if (Flag == 0 || Flag == NonZeroFlag) 148 continue; 149 error(toString(F) + ": ABI version " + Twine(Flag) + 150 " is not compatible with ABI version " + Twine(NonZeroFlag) + 151 " output"); 152 return 0; 153 } 154 155 if (NonZeroFlag == 1) { 156 error("PPC64 V1 ABI not supported"); 157 return 0; 158 } 159 160 return 2; 161 } 162 163 void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const { 164 // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement. 165 // The general dynamic code sequence for a global `x` will look like: 166 // Instruction Relocation Symbol 167 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 168 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 169 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 170 // R_PPC64_REL24 __tls_get_addr 171 // nop None None 172 173 // Relaxing to local exec entails converting: 174 // addis r3, r2, x@got@tlsgd@ha into nop 175 // addi r3, r3, x@got@tlsgd@l into addis r3, r13, x@tprel@ha 176 // bl __tls_get_addr(x@tlsgd) into nop 177 // nop into addi r3, r3, x@tprel@l 178 179 uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U; 180 181 switch (Type) { 182 case R_PPC64_GOT_TLSGD16_HA: 183 write32(Loc - EndianOffset, 0x60000000); // nop 184 break; 185 case R_PPC64_GOT_TLSGD16_LO: 186 write32(Loc - EndianOffset, 0x3c6d0000); // addis r3, r13 187 relocateOne(Loc, R_PPC64_TPREL16_HA, Val); 188 break; 189 case R_PPC64_TLSGD: 190 write32(Loc, 0x60000000); // nop 191 write32(Loc + 4, 0x38630000); // addi r3, r3 192 relocateOne(Loc + 4 + EndianOffset, R_PPC64_TPREL16_LO, Val); 193 break; 194 default: 195 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 196 } 197 } 198 199 RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S, 200 const uint8_t *Loc) const { 201 switch (Type) { 202 case R_PPC64_TOC16: 203 case R_PPC64_TOC16_DS: 204 case R_PPC64_TOC16_HA: 205 case R_PPC64_TOC16_HI: 206 case R_PPC64_TOC16_LO: 207 case R_PPC64_TOC16_LO_DS: 208 return R_GOTREL; 209 case R_PPC64_TOC: 210 return R_PPC_TOC; 211 case R_PPC64_REL24: 212 return R_PPC_CALL_PLT; 213 case R_PPC64_REL16_LO: 214 case R_PPC64_REL16_HA: 215 case R_PPC64_REL32: 216 case R_PPC64_REL64: 217 return R_PC; 218 case R_PPC64_GOT_TLSGD16: 219 case R_PPC64_GOT_TLSGD16_HA: 220 case R_PPC64_GOT_TLSGD16_HI: 221 case R_PPC64_GOT_TLSGD16_LO: 222 return R_TLSGD_GOT; 223 case R_PPC64_GOT_TLSLD16: 224 case R_PPC64_GOT_TLSLD16_HA: 225 case R_PPC64_GOT_TLSLD16_HI: 226 case R_PPC64_GOT_TLSLD16_LO: 227 return R_TLSLD_GOT; 228 case R_PPC64_GOT_TPREL16_HA: 229 case R_PPC64_GOT_TPREL16_LO_DS: 230 case R_PPC64_GOT_TPREL16_DS: 231 case R_PPC64_GOT_TPREL16_HI: 232 return R_GOT_OFF; 233 case R_PPC64_GOT_DTPREL16_HA: 234 case R_PPC64_GOT_DTPREL16_LO_DS: 235 case R_PPC64_GOT_DTPREL16_DS: 236 case R_PPC64_GOT_DTPREL16_HI: 237 return R_TLSLD_GOT_OFF; 238 case R_PPC64_TPREL16: 239 case R_PPC64_TPREL16_HA: 240 case R_PPC64_TPREL16_LO: 241 case R_PPC64_TPREL16_HI: 242 case R_PPC64_TPREL16_DS: 243 case R_PPC64_TPREL16_LO_DS: 244 case R_PPC64_TPREL16_HIGHER: 245 case R_PPC64_TPREL16_HIGHERA: 246 case R_PPC64_TPREL16_HIGHEST: 247 case R_PPC64_TPREL16_HIGHESTA: 248 return R_TLS; 249 case R_PPC64_DTPREL16: 250 case R_PPC64_DTPREL16_DS: 251 case R_PPC64_DTPREL16_HA: 252 case R_PPC64_DTPREL16_HI: 253 case R_PPC64_DTPREL16_HIGHER: 254 case R_PPC64_DTPREL16_HIGHERA: 255 case R_PPC64_DTPREL16_HIGHEST: 256 case R_PPC64_DTPREL16_HIGHESTA: 257 case R_PPC64_DTPREL16_LO: 258 case R_PPC64_DTPREL16_LO_DS: 259 case R_PPC64_DTPREL64: 260 return R_ABS; 261 case R_PPC64_TLSGD: 262 return R_TLSDESC_CALL; 263 case R_PPC64_TLSLD: 264 case R_PPC64_TLS: 265 return R_HINT; 266 default: 267 return R_ABS; 268 } 269 } 270 271 void PPC64::writeGotHeader(uint8_t *Buf) const { 272 write64(Buf, getPPC64TocBase()); 273 } 274 275 void PPC64::writePltHeader(uint8_t *Buf) const { 276 // The generic resolver stub goes first. 277 write32(Buf + 0, 0x7c0802a6); // mflr r0 278 write32(Buf + 4, 0x429f0005); // bcl 20,4*cr7+so,8 <_glink+0x8> 279 write32(Buf + 8, 0x7d6802a6); // mflr r11 280 write32(Buf + 12, 0x7c0803a6); // mtlr r0 281 write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12 282 write32(Buf + 20, 0x380cffcc); // subi r0,r12,52 283 write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2 284 write32(Buf + 28, 0xe98b002c); // ld r12,44(r11) 285 write32(Buf + 32, 0x7d6c5a14); // add r11,r12,r11 286 write32(Buf + 36, 0xe98b0000); // ld r12,0(r11) 287 write32(Buf + 40, 0xe96b0008); // ld r11,8(r11) 288 write32(Buf + 44, 0x7d8903a6); // mtctr r12 289 write32(Buf + 48, 0x4e800420); // bctr 290 291 // The 'bcl' instruction will set the link register to the address of the 292 // following instruction ('mflr r11'). Here we store the offset from that 293 // instruction to the first entry in the GotPlt section. 294 int64_t GotPltOffset = InX::GotPlt->getVA() - (InX::Plt->getVA() + 8); 295 write64(Buf + 52, GotPltOffset); 296 } 297 298 void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 299 uint64_t PltEntryAddr, int32_t Index, 300 unsigned RelOff) const { 301 int32_t Offset = PltHeaderSize + Index * PltEntrySize; 302 // bl __glink_PLTresolve 303 write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc)); 304 } 305 306 static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) { 307 // Relocations relative to the toc-base need to be adjusted by the Toc offset. 308 uint64_t TocBiasedVal = Val - PPC64TocOffset; 309 // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset. 310 uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset; 311 312 switch (Type) { 313 // TOC biased relocation. 314 case R_PPC64_GOT_TLSGD16: 315 case R_PPC64_GOT_TLSLD16: 316 case R_PPC64_TOC16: 317 return {R_PPC64_ADDR16, TocBiasedVal}; 318 case R_PPC64_TOC16_DS: 319 case R_PPC64_GOT_TPREL16_DS: 320 case R_PPC64_GOT_DTPREL16_DS: 321 return {R_PPC64_ADDR16_DS, TocBiasedVal}; 322 case R_PPC64_GOT_TLSGD16_HA: 323 case R_PPC64_GOT_TLSLD16_HA: 324 case R_PPC64_GOT_TPREL16_HA: 325 case R_PPC64_GOT_DTPREL16_HA: 326 case R_PPC64_TOC16_HA: 327 return {R_PPC64_ADDR16_HA, TocBiasedVal}; 328 case R_PPC64_GOT_TLSGD16_HI: 329 case R_PPC64_GOT_TLSLD16_HI: 330 case R_PPC64_GOT_TPREL16_HI: 331 case R_PPC64_GOT_DTPREL16_HI: 332 case R_PPC64_TOC16_HI: 333 return {R_PPC64_ADDR16_HI, TocBiasedVal}; 334 case R_PPC64_GOT_TLSGD16_LO: 335 case R_PPC64_GOT_TLSLD16_LO: 336 case R_PPC64_TOC16_LO: 337 return {R_PPC64_ADDR16_LO, TocBiasedVal}; 338 case R_PPC64_TOC16_LO_DS: 339 case R_PPC64_GOT_TPREL16_LO_DS: 340 case R_PPC64_GOT_DTPREL16_LO_DS: 341 return {R_PPC64_ADDR16_LO_DS, TocBiasedVal}; 342 343 // Dynamic Thread pointer biased relocation types. 344 case R_PPC64_DTPREL16: 345 return {R_PPC64_ADDR16, DTPBiasedVal}; 346 case R_PPC64_DTPREL16_DS: 347 return {R_PPC64_ADDR16_DS, DTPBiasedVal}; 348 case R_PPC64_DTPREL16_HA: 349 return {R_PPC64_ADDR16_HA, DTPBiasedVal}; 350 case R_PPC64_DTPREL16_HI: 351 return {R_PPC64_ADDR16_HI, DTPBiasedVal}; 352 case R_PPC64_DTPREL16_HIGHER: 353 return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal}; 354 case R_PPC64_DTPREL16_HIGHERA: 355 return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal}; 356 case R_PPC64_DTPREL16_HIGHEST: 357 return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal}; 358 case R_PPC64_DTPREL16_HIGHESTA: 359 return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal}; 360 case R_PPC64_DTPREL16_LO: 361 return {R_PPC64_ADDR16_LO, DTPBiasedVal}; 362 case R_PPC64_DTPREL16_LO_DS: 363 return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal}; 364 case R_PPC64_DTPREL64: 365 return {R_PPC64_ADDR64, DTPBiasedVal}; 366 367 default: 368 return {Type, Val}; 369 } 370 } 371 372 void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 373 // For a TOC-relative relocation, proceed in terms of the corresponding 374 // ADDR16 relocation type. 375 std::tie(Type, Val) = toAddr16Rel(Type, Val); 376 377 switch (Type) { 378 case R_PPC64_ADDR14: { 379 checkAlignment(Loc, Val, 4, Type); 380 // Preserve the AA/LK bits in the branch instruction 381 uint8_t AALK = Loc[3]; 382 write16(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 383 break; 384 } 385 case R_PPC64_ADDR16: 386 case R_PPC64_TPREL16: 387 checkInt(Loc, Val, 16, Type); 388 write16(Loc, Val); 389 break; 390 case R_PPC64_ADDR16_DS: 391 case R_PPC64_TPREL16_DS: 392 checkInt(Loc, Val, 16, Type); 393 write16(Loc, (read16(Loc) & 3) | (Val & ~3)); 394 break; 395 case R_PPC64_ADDR16_HA: 396 case R_PPC64_REL16_HA: 397 case R_PPC64_TPREL16_HA: 398 write16(Loc, ha(Val)); 399 break; 400 case R_PPC64_ADDR16_HI: 401 case R_PPC64_REL16_HI: 402 case R_PPC64_TPREL16_HI: 403 write16(Loc, hi(Val)); 404 break; 405 case R_PPC64_ADDR16_HIGHER: 406 case R_PPC64_TPREL16_HIGHER: 407 write16(Loc, higher(Val)); 408 break; 409 case R_PPC64_ADDR16_HIGHERA: 410 case R_PPC64_TPREL16_HIGHERA: 411 write16(Loc, highera(Val)); 412 break; 413 case R_PPC64_ADDR16_HIGHEST: 414 case R_PPC64_TPREL16_HIGHEST: 415 write16(Loc, highest(Val)); 416 break; 417 case R_PPC64_ADDR16_HIGHESTA: 418 case R_PPC64_TPREL16_HIGHESTA: 419 write16(Loc, highesta(Val)); 420 break; 421 case R_PPC64_ADDR16_LO: 422 case R_PPC64_REL16_LO: 423 case R_PPC64_TPREL16_LO: 424 write16(Loc, lo(Val)); 425 break; 426 case R_PPC64_ADDR16_LO_DS: 427 case R_PPC64_TPREL16_LO_DS: 428 write16(Loc, (read16(Loc) & 3) | (lo(Val) & ~3)); 429 break; 430 case R_PPC64_ADDR32: 431 case R_PPC64_REL32: 432 checkInt(Loc, Val, 32, Type); 433 write32(Loc, Val); 434 break; 435 case R_PPC64_ADDR64: 436 case R_PPC64_REL64: 437 case R_PPC64_TOC: 438 write64(Loc, Val); 439 break; 440 case R_PPC64_REL24: { 441 uint32_t Mask = 0x03FFFFFC; 442 checkInt(Loc, Val, 24, Type); 443 write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask)); 444 break; 445 } 446 case R_PPC64_DTPREL64: 447 write64(Loc, Val - DynamicThreadPointerOffset); 448 break; 449 default: 450 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 451 } 452 } 453 454 bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 455 uint64_t BranchAddr, const Symbol &S) const { 456 // If a function is in the plt it needs to be called through 457 // a call stub. 458 return Type == R_PPC64_REL24 && S.isInPlt(); 459 } 460 461 RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data, 462 RelExpr Expr) const { 463 if (Expr == R_RELAX_TLS_GD_TO_IE) 464 return R_RELAX_TLS_GD_TO_IE_GOT_OFF; 465 return Expr; 466 } 467 468 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement. 469 // The general dynamic code sequence for a global `x` uses 4 instructions. 470 // Instruction Relocation Symbol 471 // addis r3, r2, x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x 472 // addi r3, r3, x@got@tlsgd@l R_PPC64_GOT_TLSGD16_LO x 473 // bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x 474 // R_PPC64_REL24 __tls_get_addr 475 // nop None None 476 // 477 // Relaxing to initial-exec entails: 478 // 1) Convert the addis/addi pair that builds the address of the tls_index 479 // struct for 'x' to an addis/ld pair that loads an offset from a got-entry. 480 // 2) Convert the call to __tls_get_addr to a nop. 481 // 3) Convert the nop following the call to an add of the loaded offset to the 482 // thread pointer. 483 // Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is 484 // used as the relaxation hint for both steps 2 and 3. 485 void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const { 486 switch (Type) { 487 case R_PPC64_GOT_TLSGD16_HA: 488 // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to 489 // addis rT, r2, sym@got@tprel@ha. 490 relocateOne(Loc, R_PPC64_GOT_TPREL16_HA, Val); 491 return; 492 case R_PPC64_GOT_TLSGD16_LO: { 493 // Relax from addi r3, rA, sym@got@tlsgd@l to 494 // ld r3, sym@got@tprel@l(rA) 495 uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U; 496 uint32_t InputRegister = (read32(Loc - EndianOffset) & (0x1f << 16)); 497 write32(Loc - EndianOffset, 0xE8600000 | InputRegister); 498 relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val); 499 return; 500 } 501 case R_PPC64_TLSGD: 502 write32(Loc, 0x60000000); // bl __tls_get_addr(sym@tlsgd) --> nop 503 write32(Loc + 4, 0x7c636A14); // nop --> add r3, r3, r13 504 return; 505 default: 506 llvm_unreachable("unsupported relocation for TLS GD to IE relaxation"); 507 } 508 } 509 510 TargetInfo *elf::getPPC64TargetInfo() { 511 static PPC64 Target; 512 return &Target; 513 } 514