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Searched refs:getSubRegFromChannel (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp210 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
215 unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
216 unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
225 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
H A DR600RegisterInfo.h27 static unsigned getSubRegFromChannel(unsigned Channel);
H A DR600RegisterInfo.cpp24 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { in getSubRegFromChannel() function in R600RegisterInfo
H A DR600ControlFlowFinalizer.cpp281 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
290 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
H A DSIRegisterInfo.h67 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
H A DSIShrinkInstructions.cpp545 Reg = TRI->getSubReg(Reg, TRI->getSubRegFromChannel(I)); in getSubRegForIndex()
547 Sub = TRI->getSubRegFromChannel(I + TRI->getChannelFromSubReg(Sub)); in getSubRegForIndex()
H A DSIFixSGPRCopies.cpp1154 TRI->getSubRegFromChannel(i), &AMDGPU::VGPR_32RegClass); in lowerVGPR2SGPRCopies()
1160 Result.addReg(PartialDst).addImm(TRI->getSubRegFromChannel(i)); in lowerVGPR2SGPRCopies()
H A DSIRegisterInfo.cpp529 unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel, in getSubRegFromChannel() function in SIRegisterInfo
1486 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore()
1517 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1544 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore()
H A DAMDGPUISelDAGToDAG.cpp484 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector()
485 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
495 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector()
496 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
H A DSIInstrInfo.cpp687 SubIdx = RI.getSubRegFromChannel(Channel, 2); in expandSGPRCopy()
5296 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5305 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5509 .addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx)); in emitLoadSRsrcFromVGPRLoop()
5513 .addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx + 1)); in emitLoadSRsrcFromVGPRLoop()
5533 Cmp.addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx, 2)); in emitLoadSRsrcFromVGPRLoop()
5555 .addImm(TRI->getSubRegFromChannel(Channel++)); in emitLoadSRsrcFromVGPRLoop()
H A DR600InstrInfo.cpp59 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(I); in copyPhysReg()
H A DAMDGPUInstructionSelector.cpp509 unsigned SubReg = SIRegisterInfo::getSubRegFromChannel(Offset / 32, in selectG_EXTRACT()
749 unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32, InsSize / 32); in selectG_INSERT()
H A DSIISelLowering.cpp3737 return std::make_pair(SIRegisterInfo::getSubRegFromChannel(Offset), 0); in computeIndirectRegAndOffset()
11935 .addImm(SIRegisterInfo::getSubRegFromChannel(CurrIdx)); in AddIMGInit()