| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600TargetTransformInfo.h | 52 unsigned getMinVectorRegisterBitWidth() const;
|
| H A D | R600TargetTransformInfo.cpp | 44 unsigned R600TTIImpl::getMinVectorRegisterBitWidth() const { return 32; } in getMinVectorRegisterBitWidth() function in R600TTIImpl
|
| H A D | AMDGPUTargetTransformInfo.h | 117 unsigned getMinVectorRegisterBitWidth() const;
|
| H A D | AMDGPUTargetTransformInfo.cpp | 321 unsigned GCNTTIImpl::getMinVectorRegisterBitWidth() const { in getMinVectorRegisterBitWidth() function in GCNTTIImpl
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetTransformInfo.h | 82 unsigned getMinVectorRegisterBitWidth() const { return 32; } in getMinVectorRegisterBitWidth() function
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.h | 130 unsigned getMinVectorRegisterBitWidth() const { in getMinVectorRegisterBitWidth() function
131 return ST->getMinVectorRegisterBitWidth(); in getMinVectorRegisterBitWidth()
|
| H A D | AArch64Subtarget.h | 194 unsigned getMinVectorRegisterBitWidth() const { in getMinVectorRegisterBitWidth() function
|
| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VETargetTransformInfo.h | 120 unsigned getMinVectorRegisterBitWidth() const { in getMinVectorRegisterBitWidth() function
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 108 return TypeSize::getFixed(getMinVectorRegisterBitWidth()); in getRegisterBitWidth()
116 unsigned HexagonTTIImpl::getMinVectorRegisterBitWidth() const { in getMinVectorRegisterBitWidth() function in HexagonTTIImpl
|
| H A D | HexagonTargetTransformInfo.h | 86 unsigned getMinVectorRegisterBitWidth() const;
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.h | 82 unsigned getMinVectorRegisterBitWidth() const { in getMinVectorRegisterBitWidth() function
|
| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 946 unsigned getMinVectorRegisterBitWidth() const;
1672 virtual unsigned getMinVectorRegisterBitWidth() const = 0;
2173 unsigned getMinVectorRegisterBitWidth() const override { in getMinVectorRegisterBitWidth() function
2174 return Impl.getMinVectorRegisterBitWidth(); in getMinVectorRegisterBitWidth()
|
| H A D | TargetTransformInfoImpl.h | 422 unsigned getMinVectorRegisterBitWidth() const { return 128; } in getMinVectorRegisterBitWidth() function
|
| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 635 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const { in getMinVectorRegisterBitWidth() function in TargetTransformInfo
636 return TTIImpl->getMinVectorRegisterBitWidth(); in getMinVectorRegisterBitWidth()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 163 unsigned MinVectorSize = TTI.getMinVectorRegisterBitWidth(); in vectorizeLoadInsert()
|
| H A D | SLPVectorizer.cpp | 875 MinVecRegSize = TTI->getMinVectorRegisterBitWidth(); in BoUpSLP()
|