| /llvm-project-15.0.7/llvm/include/llvm/Transforms/Instrumentation/ |
| H A D | AddressSanitizerCommon.h | 28 bool IsWrite; variable
35 InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
38 : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment), in IsWrite() argument
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| H A D | AddressSanitizer.h | 58 const bool IsWrite; member
62 ASanAccessInfo(bool IsWrite, bool CompileKernel, uint8_t AccessSizeIndex);
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| /llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemProfiler.cpp | 157 bool IsWrite; member
184 bool IsWrite);
339 Access.IsWrite = false; in isInterestingMemoryAccess()
345 Access.IsWrite = true; in isInterestingMemoryAccess()
351 Access.IsWrite = true; in isInterestingMemoryAccess()
357 Access.IsWrite = true; in isInterestingMemoryAccess()
371 Access.IsWrite = true; in isInterestingMemoryAccess()
376 Access.IsWrite = false; in isInterestingMemoryAccess()
455 IsWrite); in instrumentMaskedLoadOrStore()
463 if (Access.IsWrite) in instrumentMop()
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| H A D | ThreadSanitizer.cpp | 432 const bool IsWrite = isa<StoreInst>(*I); in chooseInstructionsToInstrument() local
433 Value *Addr = IsWrite ? cast<StoreInst>(I)->getPointerOperand() in chooseInstructionsToInstrument()
439 if (!IsWrite) { in chooseInstructionsToInstrument()
474 if (IsWrite) { in chooseInstructionsToInstrument()
600 const bool IsWrite = isa<StoreInst>(*II.Inst); in instrumentLoadOrStore() local
614 if (IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
632 if (!IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
656 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; in instrumentLoadOrStore()
661 OnAccessFunc = IsWrite ? TsanUnalignedVolatileWrite[Idx] in instrumentLoadOrStore()
667 if (IsCompoundRW || IsWrite) in instrumentLoadOrStore()
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| H A D | AddressSanitizer.cpp | 603 IsWrite((Packed >> kIsWriteShift) & kIsWriteMask), in ASanAccessInfo()
606 ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel, in ASanAccessInfo() argument
608 : Packed((IsWrite << kIsWriteShift) + in ASanAccessInfo()
611 AccessSizeIndex(AccessSizeIndex), IsWrite(IsWrite), in ASanAccessInfo()
1302 unsigned OpOffset = IsWrite ? 1 : 0; in getInterestingMemoryOperands()
1303 if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads) in getInterestingMemoryOperands()
1479 if (O.IsWrite) in instrumentMop()
1506 Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][0], in generateCrashCode()
1509 Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][1], in generateCrashCode()
1544 uint32_t TypeSize, bool IsWrite, Value *SizeArgument) { in instrumentAMDGPUAddress() argument
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| H A D | HWAddressSanitizer.cpp | 296 int64_t getAccessInfo(bool IsWrite, unsigned AccessSizeIndex);
297 void instrumentMemAccessOutline(Value *Ptr, bool IsWrite,
300 void instrumentMemAccessInline(Value *Ptr, bool IsWrite,
813 int64_t HWAddressSanitizer::getAccessInfo(bool IsWrite, in getAccessInfo() argument
819 (IsWrite << HWASanAccessInfo::IsWriteShift) + in getAccessInfo()
823 void HWAddressSanitizer::instrumentMemAccessOutline(Value *Ptr, bool IsWrite, in instrumentMemAccessOutline() argument
827 const int64_t AccessInfo = getAccessInfo(IsWrite, AccessSizeIndex); in instrumentMemAccessOutline()
838 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline() argument
842 const int64_t AccessInfo = getAccessInfo(IsWrite, AccessSizeIndex); in instrumentMemAccessInline()
963 IRB.CreateCall(HwasanMemoryAccessCallback[O.IsWrite][AccessSizeIndex], in instrumentMemAccess()
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| /llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/ |
| H A D | tsan_shadow.h | 122 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
168 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
193 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
200 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
207 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| H A D | tsan_rtl_report.cpp | 184 mop->write = s.IsWrite(); in AddMemoryAccess()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | LoopAccessAnalysis.cpp | 977 bool IsWrite = Access.getInt(); in createCheckForAccess() local
978 RtCheck.insert(TheLoop, Ptr, PtrExpr, AccessTy, IsWrite, DepId, ASId, PSE, in createCheckForAccess()
1020 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
1022 if (IsWrite) in canCheckPtrAtRT()
1026 AccessInfos.emplace_back(Ptr, IsWrite); in canCheckPtrAtRT()
1191 bool IsWrite = AC.first.getInt(); in processMemAccesses() local
1195 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
1200 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
1204 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
1223 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
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| /llvm-project-15.0.7/llvm/lib/Transforms/IPO/ |
| H A D | FunctionAttrs.cpp | 676 bool IsWrite = false; in determinePointerAccessAttrs() local
684 if (IsWrite && IsRead) in determinePointerAccessAttrs()
750 IsWrite = true; in determinePointerAccessAttrs()
776 IsWrite = true; in determinePointerAccessAttrs()
788 if (IsWrite && IsRead) in determinePointerAccessAttrs()
792 else if (IsWrite) in determinePointerAccessAttrs()
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | LoopAccessAnalysis.h | 249 ArrayRef<unsigned> getOrderForAccess(Value *Ptr, bool IsWrite) const { in getOrderForAccess() argument
250 auto I = Accesses.find({Ptr, IsWrite}); in getOrderForAccess()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 1356 StringRef Name = AccessInfo.IsWrite ? "store" : "load"; in LowerASAN_CHECK_MEMACCESS()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4428 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in lowerPREFETCH() local
4429 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ; in lowerPREFETCH()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3660 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in LowerPREFETCH() local
3676 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in LowerPREFETCH()
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