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/linux-6.15/arch/sparc/include/uapi/asm/
H A Dpstate.h19 #define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable */
20 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
30 #define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege. */
55 #define TSTATE_PSTATE _AC(0x00000000000fff00,UL) /* PSTATE. */
62 #define TSTATE_MG _AC(0x0000000000040000,UL) /* MMU Globals. */
66 #define TSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TSO */
67 #define TSTATE_PSO _AC(0x0000000000004000,UL) /* MM: PSO */
68 #define TSTATE_RMO _AC(0x0000000000008000,UL) /* MM: RMO */
85 #define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */
86 #define FPRS_DU _AC(0x0000000000000002,UL) /* Dirty Upper. */
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/linux-6.15/tools/arch/arm64/include/asm/
H A Desr.h12 #define ESR_ELx_EC_UNKNOWN UL(0x00)
13 #define ESR_ELx_EC_WFx UL(0x01)
15 #define ESR_ELx_EC_CP15_32 UL(0x03)
16 #define ESR_ELx_EC_CP15_64 UL(0x04)
17 #define ESR_ELx_EC_CP14_MR UL(0x05)
18 #define ESR_ELx_EC_CP14_LS UL(0x06)
24 #define ESR_ELx_EC_BTI UL(0x0D)
25 #define ESR_ELx_EC_ILL UL(0x0E)
27 #define ESR_ELx_EC_SVC32 UL(0x11)
35 #define ESR_ELx_EC_SVE UL(0x19)
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/linux-6.15/arch/arm64/include/asm/
H A Desr.h13 #define ESR_ELx_EC_UNKNOWN UL(0x00)
14 #define ESR_ELx_EC_WFx UL(0x01)
16 #define ESR_ELx_EC_CP15_32 UL(0x03)
17 #define ESR_ELx_EC_CP15_64 UL(0x04)
18 #define ESR_ELx_EC_CP14_MR UL(0x05)
19 #define ESR_ELx_EC_CP14_LS UL(0x06)
25 #define ESR_ELx_EC_BTI UL(0x0D)
26 #define ESR_ELx_EC_ILL UL(0x0E)
28 #define ESR_ELx_EC_SVC32 UL(0x11)
36 #define ESR_ELx_EC_SVE UL(0x19)
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H A Dpgtable-hwdef.h308 #define TCR_A1 (UL(1) << 22)
310 #define TCR_TBI0 (UL(1) << 37)
311 #define TCR_TBI1 (UL(1) << 38)
312 #define TCR_HA (UL(1) << 39)
313 #define TCR_HD (UL(1) << 40)
318 #define TCR_TBID0 (UL(1) << 51)
319 #define TCR_TBID1 (UL(1) << 52)
320 #define TCR_NFD0 (UL(1) << 53)
321 #define TCR_NFD1 (UL(1) << 54)
322 #define TCR_E0PD0 (UL(1) << 55)
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H A Dkvm_arm.h17 #define HCR_TID5 (UL(1) << 58)
18 #define HCR_DCT (UL(1) << 57)
24 #define HCR_TOCU (UL(1) << 52)
27 #define HCR_TID4 (UL(1) << 49)
28 #define HCR_FIEN (UL(1) << 47)
29 #define HCR_FWB (UL(1) << 46)
31 #define HCR_AT (UL(1) << 44)
33 #define HCR_NV (UL(1) << 42)
40 #define HCR_ID (UL(1) << 33)
41 #define HCR_CD (UL(1) << 32)
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H A Drsi_smc.h21 #define RSI_ABI_VERSION_MAJOR UL(1)
27 #define RSI_ABI_VERSION_MINOR UL(0)
35 #define RSI_SUCCESS UL(0)
36 #define RSI_ERROR_INPUT UL(1)
37 #define RSI_ERROR_STATE UL(2)
38 #define RSI_INCOMPLETE UL(3)
39 #define RSI_ERROR_UNKNOWN UL(4)
168 #define RSI_NO_CHANGE_DESTROYED UL(0)
169 #define RSI_CHANGE_DESTROYED UL(1)
171 #define RSI_ACCEPT UL(0)
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/linux-6.15/arch/riscv/include/asm/
H A Dcsr.h22 #define SR_FS_OFF _AC(0x00000000, UL)
24 #define SR_FS_CLEAN _AC(0x00004000, UL)
25 #define SR_FS_DIRTY _AC(0x00006000, UL)
28 #define SR_VS_OFF _AC(0x00000000, UL)
40 #define SR_XS_OFF _AC(0x00000000, UL)
61 #define SATP_PPN _AC(0x003FFFFF, UL)
66 #define SATP_ASID_MASK _AC(0x1FF, UL)
147 #define HGATP_MODE_OFF _AC(0, UL)
181 (_AC(1, UL) << IRQ_S_EXT) | \
182 (_AC(1, UL) << IRQ_PMU_OVF))
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/linux-6.15/tools/arch/riscv/include/asm/
H A Dcsr.h21 #define SR_FS_OFF _AC(0x00000000, UL)
23 #define SR_FS_CLEAN _AC(0x00004000, UL)
24 #define SR_FS_DIRTY _AC(0x00006000, UL)
27 #define SR_VS_OFF _AC(0x00000000, UL)
29 #define SR_VS_CLEAN _AC(0x00000400, UL)
33 #define SR_XS_OFF _AC(0x00000000, UL)
54 #define SATP_PPN _AC(0x003FFFFF, UL)
59 #define SATP_ASID_MASK _AC(0x1FF, UL)
136 #define HGATP_MODE_OFF _AC(0, UL)
170 (_AC(1, UL) << IRQ_S_EXT))
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/linux-6.15/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
51 #define PERIP_GRP2_BASE UL(0xB3000000)
53 #define MCIF_SDHCI_BASE UL(0xB3000000)
54 #define SYSRAM0_BASE UL(0xB3800000)
60 #define UART_BASE UL(0xE0000000)
62 #define SSP_BASE UL(0xE0100000)
63 #define MISC_BASE UL(0xE0700000)
77 #define L2CC_BASE UL(0xED000000)
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/linux-6.15/arch/s390/include/uapi/asm/
H A Dptrace.h173 #define PSW_MASK_PER _AC(0x40000000, UL)
174 #define PSW_MASK_DAT _AC(0x04000000, UL)
175 #define PSW_MASK_IO _AC(0x02000000, UL)
176 #define PSW_MASK_EXT _AC(0x01000000, UL)
177 #define PSW_MASK_KEY _AC(0x00F00000, UL)
182 #define PSW_MASK_ASC _AC(0x0000C000, UL)
183 #define PSW_MASK_CC _AC(0x00003000, UL)
184 #define PSW_MASK_PM _AC(0x00000F00, UL)
185 #define PSW_MASK_RI _AC(0x00000000, UL)
186 #define PSW_MASK_EA _AC(0x00000000, UL)
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/linux-6.15/arch/sparc/include/asm/
H A Ddcu.h8 #define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
9 #define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
10 #define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
11 #define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
12 #define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
13 #define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
14 #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
16 #define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
23 #define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
24 #define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
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H A Dsfafsr.h9 #define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
11 #define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
15 #define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
19 #define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
25 #define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
27 #define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
31 #define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT)
33 #define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT)
44 #define UDBE_UE (_AC(1,UL) << 9)
45 #define UDBE_CE (_AC(1,UL) << 8)
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H A Dpgtable_64.h37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
40 #define MODULES_VADDR _AC(0x0000000010000000,UL)
41 #define MODULES_LEN _AC(0x00000000e0000000,UL)
42 #define MODULES_END _AC(0x00000000f0000000,UL)
52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
60 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT)
66 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
225 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); in pfn_pte()
276 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); in pte_modify()
797 return pmd_val(pmd) != 0UL; in pmd_present()
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H A Dlsu.h8 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
9 #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
10 #define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
11 #define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
12 #define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
13 #define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
14 #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
15 #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
16 #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
17 #define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
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H A Dmmu_64.h11 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
20 #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
22 #define CTX_PGSZ_8KB _AC(0x0,UL)
23 #define CTX_PGSZ_64KB _AC(0x1,UL)
24 #define CTX_PGSZ_512KB _AC(0x2,UL)
25 #define CTX_PGSZ_4MB _AC(0x3,UL)
26 #define CTX_PGSZ_BITS _AC(0x7,UL)
/linux-6.15/tools/testing/selftests/kvm/include/arm64/
H A Dprocessor.h47 #define MAIR_ATTR_DEVICE_GRE UL(0x0c)
48 #define MAIR_ATTR_NORMAL_WT UL(0xbb)
84 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
85 #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
88 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
89 #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
90 #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
91 #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
94 #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
100 #define TCR_HA (UL(1) << 39)
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/linux-6.15/arch/sparc/kernel/
H A Dtraps_32.c152 { ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
153 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
154 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
155 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL };
/linux-6.15/arch/s390/include/asm/
H A Dptrace.h24 #define PSW32_MASK_PER _AC(0x40000000, UL)
25 #define PSW32_MASK_DAT _AC(0x04000000, UL)
26 #define PSW32_MASK_IO _AC(0x02000000, UL)
27 #define PSW32_MASK_EXT _AC(0x01000000, UL)
28 #define PSW32_MASK_KEY _AC(0x00F00000, UL)
31 #define PSW32_MASK_WAIT _AC(0x00020000, UL)
33 #define PSW32_MASK_ASC _AC(0x0000C000, UL)
34 #define PSW32_MASK_CC _AC(0x00003000, UL)
35 #define PSW32_MASK_PM _AC(0x00000f00, UL)
36 #define PSW32_MASK_RI _AC(0x00000080, UL)
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/linux-6.15/arch/mips/include/asm/mach-generic/
H A Dspaces.h28 # define PHYS_OFFSET _AC(0, UL)
33 #define CAC_BASE _AC(0x80000000, UL)
35 #define IO_BASE _AC(0xa0000000, UL)
38 #define UNCAC_BASE _AC(0xa0000000, UL)
42 #define MAP_BASE _AC(0xc0000000, UL)
49 #define HIGHMEM_START _AC(0x20000000, UL)
63 #define IO_BASE _AC(0x9000000000000000, UL)
67 #define UNCAC_BASE _AC(0x9000000000000000, UL)
71 #define MAP_BASE _AC(0xc000000000000000, UL)
80 #define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
/linux-6.15/arch/x86/include/asm/
H A Dpgtable_64_types.h65 #define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
99 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
101 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
103 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
197 # define MODULES_END _AC(0xffffffffff000000, UL)
199 # define MODULES_END _AC(0xfffffffffe000000, UL)
203 #define ESPFIX_PGD_ENTRY _AC(-2, UL)
206 #define CPU_ENTRY_AREA_PGD _AC(-4, UL)
209 #define EFI_VA_START ( -4 * (_AC(1, UL) << 30))
210 #define EFI_VA_END (-68 * (_AC(1, UL) << 30))
/linux-6.15/arch/mips/include/asm/mach-ip27/
H A Dspaces.h21 #define HSPEC_BASE _AC(0x9000000000000000, UL)
22 #define IO_BASE _AC(0x9200000000000000, UL)
23 #define MSPEC_BASE _AC(0x9400000000000000, UL)
24 #define UNCAC_BASE _AC(0x9600000000000000, UL)
25 #define CAC_BASE _AC(0xa800000000000000, UL)
31 #define HIGHMEM_START (~0UL)
/linux-6.15/arch/arm/include/asm/
H A Dmemory.h34 #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
44 #define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
53 #define TASK_SIZE_26 (UL(1) << 26)
86 #define FDT_FIXED_BASE UL(0xff800000)
97 #define VECTORS_BASE UL(0xffff0000)
113 #define TASK_SIZE UL(0xffffffff)
116 #define TASK_UNMAPPED_BASE UL(0x00000000)
120 #define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
146 #define ITCM_OFFSET UL(0xfffe0000)
147 #define DTCM_OFFSET UL(0xfffe8000)
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/linux-6.15/tools/memory-model/
H A Dlock.cat20 * UL Unlock: a spin_unlock() event
28 * LKW and UL are write events; UL has Release ordering.
73 let Release = Release | UL
76 (* Match LKW events to their corresponding UL events *)
77 let critical = ([LKW] ; po-loc ; [UL]) \ (po-loc ; [LKW | UL] ; po-loc)
79 flag ~empty UL \ range(critical) as unmatched-unlock
118 let possible-rf-ru e = (((UL * {e}) & po-loc) \
119 ([UL] ; po-loc ; [UL] ; po-loc)) |
120 (((UL | IW) * {e}) & loc & ext)
140 let W = W | UL
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/linux-6.15/drivers/video/fbdev/core/
H A Dfb_draw.h108 val = fb_comp(val >> 1, val << 1, ~0UL / 3); in fb_reverse_bits_long()
109 val = fb_comp(val >> 2, val << 2, ~0UL / 5); in fb_reverse_bits_long()
110 return fb_comp(val >> 4, val << 4, ~0UL / 17); in fb_reverse_bits_long()
128 return reverse.pixel ? fb_left(~0UL, index) : swab_long(fb_right(~0UL, index)); in fb_pixel_mask()
130 return reverse.pixel ? swab_long(fb_left(~0UL, index)) : fb_right(~0UL, index); in fb_pixel_mask()
132 return reverse.byte ? swab_long(fb_right(~0UL, index)) : fb_right(~0UL, index); in fb_pixel_mask()
/linux-6.15/arch/x86/mm/
H A Ddump_pagetables.c83 [LOW_KERNEL_NR] = { 0UL, "Low Kernel Mapping" },
84 [VMALLOC_START_NR] = { 0UL, "vmalloc() Area" },
85 [VMEMMAP_START_NR] = { 0UL, "Vmemmap" },
95 [LDT_NR] = { 0UL, "LDT remap" },
134 [VMALLOC_START_NR] = { 0UL, "vmalloc() Area" },
135 [VMALLOC_END_NR] = { 0UL, "vmalloc() End" },
140 [LDT_NR] = { 0UL, "LDT remap" },
142 [CPU_ENTRY_AREA_NR] = { 0UL, "CPU entry area" },
143 [FIXADDR_START_NR] = { 0UL, "Fixmap area" },
372 {GUARD_HOLE_END_ADDR, ~0UL}, in ptdump_walk_pgd_level_core()
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