Lines Matching refs:UL
56 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
66 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
73 #define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
83 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
226 #define TTBR_CNP_BIT (UL(1) << 0)
233 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
234 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
237 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
238 #define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
241 #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
243 #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
244 #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
245 #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
246 #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
247 #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
250 #define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
252 #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
253 #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
254 #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
255 #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
256 #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
266 #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
267 #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
268 #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
269 #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
270 #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
273 #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
274 #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
275 #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
276 #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
277 #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
286 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
287 #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
290 #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
291 #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
295 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
296 #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
297 #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
298 #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
301 #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
302 #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
303 #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
304 #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
307 #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
308 #define TCR_A1 (UL(1) << 22)
309 #define TCR_ASID16 (UL(1) << 36)
310 #define TCR_TBI0 (UL(1) << 37)
311 #define TCR_TBI1 (UL(1) << 38)
312 #define TCR_HA (UL(1) << 39)
313 #define TCR_HD (UL(1) << 40)
315 #define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT)
317 #define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT)
318 #define TCR_TBID0 (UL(1) << 51)
319 #define TCR_TBID1 (UL(1) << 52)
320 #define TCR_NFD0 (UL(1) << 53)
321 #define TCR_NFD1 (UL(1) << 54)
322 #define TCR_E0PD0 (UL(1) << 55)
323 #define TCR_E0PD1 (UL(1) << 56)
324 #define TCR_TCMA0 (UL(1) << 57)
325 #define TCR_TCMA1 (UL(1) << 58)
326 #define TCR_DS (UL(1) << 59)
340 #define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
341 (UL(1) << (48 - PGDIR_SHIFT))) * 8)