Lines Matching refs:UL
13 #define ESR_ELx_EC_UNKNOWN UL(0x00)
14 #define ESR_ELx_EC_WFx UL(0x01)
16 #define ESR_ELx_EC_CP15_32 UL(0x03)
17 #define ESR_ELx_EC_CP15_64 UL(0x04)
18 #define ESR_ELx_EC_CP14_MR UL(0x05)
19 #define ESR_ELx_EC_CP14_LS UL(0x06)
20 #define ESR_ELx_EC_FP_ASIMD UL(0x07)
21 #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
22 #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */
24 #define ESR_ELx_EC_CP14_64 UL(0x0C)
25 #define ESR_ELx_EC_BTI UL(0x0D)
26 #define ESR_ELx_EC_ILL UL(0x0E)
28 #define ESR_ELx_EC_SVC32 UL(0x11)
29 #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */
30 #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */
32 #define ESR_ELx_EC_SVC64 UL(0x15)
33 #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */
34 #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */
35 #define ESR_ELx_EC_SYS64 UL(0x18)
36 #define ESR_ELx_EC_SVE UL(0x19)
37 #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */
39 #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */
40 #define ESR_ELx_EC_SME UL(0x1D)
42 #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
43 #define ESR_ELx_EC_IABT_LOW UL(0x20)
44 #define ESR_ELx_EC_IABT_CUR UL(0x21)
45 #define ESR_ELx_EC_PC_ALIGN UL(0x22)
47 #define ESR_ELx_EC_DABT_LOW UL(0x24)
48 #define ESR_ELx_EC_DABT_CUR UL(0x25)
49 #define ESR_ELx_EC_SP_ALIGN UL(0x26)
50 #define ESR_ELx_EC_MOPS UL(0x27)
51 #define ESR_ELx_EC_FP_EXC32 UL(0x28)
53 #define ESR_ELx_EC_FP_EXC64 UL(0x2C)
54 #define ESR_ELx_EC_GCS UL(0x2D)
56 #define ESR_ELx_EC_SERROR UL(0x2F)
57 #define ESR_ELx_EC_BREAKPT_LOW UL(0x30)
58 #define ESR_ELx_EC_BREAKPT_CUR UL(0x31)
59 #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32)
60 #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33)
61 #define ESR_ELx_EC_WATCHPT_LOW UL(0x34)
62 #define ESR_ELx_EC_WATCHPT_CUR UL(0x35)
64 #define ESR_ELx_EC_BKPT32 UL(0x38)
66 #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */
68 #define ESR_ELx_EC_BRK64 UL(0x3C)
70 #define ESR_ELx_EC_MAX UL(0x3F)
74 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
78 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
87 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
91 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
93 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
96 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
98 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
99 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
103 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
105 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
107 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
109 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
144 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
146 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
148 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
150 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
152 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
154 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
156 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
160 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
162 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
164 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
166 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
168 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
173 #define ESR_ELx_CV (UL(1) << 24)
175 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
176 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
177 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
178 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
179 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
180 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
181 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
182 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
184 #define DISR_EL1_IDS (UL(1) << 24)
202 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
208 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
210 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
212 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
214 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
216 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
218 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
315 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
325 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
327 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
329 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
331 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
333 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
351 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
354 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
357 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
359 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
389 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
390 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
391 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
392 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
393 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
394 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
395 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)