Home
last modified time | relevance | path

Searched refs:GC_HWIP (Results 1 – 25 of 59) sorted by relevance

123

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h111 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0)
118 …uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG…
119 …uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
120 …uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC…
139 …_((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)
143 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0)
155 …uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
156 …uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
157 …uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRB…
158 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRB…
[all …]
H A Dgmc_v10_0.c147 (amdgpu_ip_version(adev, GC_HWIP, 0) < in gmc_v10_0_process_interrupt()
284 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_gpu_tlb()
315 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_gpu_tlb()
618 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_set_gfxhub_funcs()
734 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_mc_init()
801 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
819 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
1122 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || in gmc_v10_0_get_clockgating_state()
1123 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) in gmc_v10_0_get_clockgating_state()
H A Dgmc_v9_0.c669 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
679 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
915 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
1147 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); in gmc_v9_0_get_coherence_flags()
1283 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) in gmc_v9_0_override_vm_pte_flags()
1619 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_init_nps_details()
1806 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_mc_init()
2132 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_sw_init()
2225 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= in gmc_v9_0_sw_init()
2412 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && in gmc_v9_0_hw_init()
[all …]
H A Damdgpu_discovery.c214 [GC_HWIP] = GC_HWID,
1888 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_common_ip_blocks()
1935 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_common_ip_blocks()
1944 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_gmc_ip_blocks()
1990 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gmc_ip_blocks()
2245 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_gc_ip_blocks()
2293 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gc_ip_blocks()
2455 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_mes_ip_blocks()
2485 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_init_soc_config()
2752 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_ip_blocks()
[all …]
H A Dgmc_v12_0.c214 GC_HWIP : MMHUB_HWIP; in gmc_v12_0_flush_vm_hub()
535 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && in gmc_v12_0_get_dcc_alignment()
536 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) in gmc_v12_0_get_dcc_alignment()
595 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_set_gfxhub_funcs()
750 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_sw_init()
H A Dgmc_v11_0.c245 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_gpu_tlb()
593 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_set_gfxhub_funcs()
657 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && in gmc_v11_0_vram_gtt_location()
759 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
767 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
H A Dgfx_v9_0.c1071 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_init_golden_registers()
1279 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_fw_write_wait()
1396 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_if_need_gfxoff()
2026 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_gpu_early_init()
2220 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_sw_init()
2236 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_sw_init()
2624 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_init_sq_config()
3076 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v9_0_init_pg()
3190 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_rlc_resume()
4251 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_get_gpu_clock_counter()
[all …]
H A Damdgpu_vm.h123 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_P…
137 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGP…
141 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_P…
H A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
H A Damdgpu_display.c796 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
798 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in convert_tiling_flags_to_modifier()
801 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in convert_tiling_flags_to_modifier()
811 if (amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
818 if (amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
876 amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
914 if ((amdgpu_ip_version(adev, GC_HWIP, in convert_tiling_flags_to_modifier()
1273 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) in amdgpu_display_framebuffer_init()
H A Damdgpu_sdma.c532 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || in amdgpu_sdma_is_shared_inv_eng()
533 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || in amdgpu_sdma_is_shared_inv_eng()
534 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) in amdgpu_sdma_is_shared_inv_eng()
H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
H A Dgfx_v10_0.c3865 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_spm_golden_registers()
3891 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_golden_registers()
4115 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_check_fw_write_wait()
4166 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_check_gfxoff_flag()
4368 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_rlcg_reg_access_ctrl()
4582 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_gpu_early_init()
4758 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_sw_init()
4795 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_sw_init()
8229 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v10_0_update_gfx_clock_gating()
8231 (amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v10_0_update_gfx_clock_gating()
[all …]
H A Dpsp_v10_0.c61 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0)) && in psp_v10_0_init_microcode()
H A Damdgpu_amdkfd.c676 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && in amdgpu_amdkfd_set_compute_idle()
678 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) { in amdgpu_amdkfd_set_compute_idle()
681 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && in amdgpu_amdkfd_set_compute_idle()
H A Damdgpu_mes.c1527 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in amdgpu_mes_self_test()
1529 amdgpu_ip_version(adev, GC_HWIP, 0) < in amdgpu_mes_self_test()
1590 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, in amdgpu_mes_init_microcode()
1595 } else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_init_microcode()
1596 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) { in amdgpu_mes_init_microcode()
1669 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
1670 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
H A Dimu_v12_0.c49 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v12_0_init_microcode()
370 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in imu_v12_0_program_rlc_ram()
H A Dimu_v11_0.c53 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v11_0_init_microcode()
358 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in imu_v11_0_program_rlc_ram()
H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
H A Dsoc24.c262 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_need_full_reset()
388 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_common_early_init()
H A Damdgpu_device.c796 GC_HWIP, false, in amdgpu_device_xcc_rreg()
927 GC_HWIP, true, in amdgpu_device_xcc_wreg()
1441 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || in amdgpu_device_asic_init()
1442 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || in amdgpu_device_asic_init()
1443 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0) || in amdgpu_device_asic_init()
1444 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { in amdgpu_device_asic_init()
3426 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0)) in amdgpu_device_smu_fini_early()
3652 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0)) in amdgpu_device_ip_suspend_phase2()
4446 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) in amdgpu_device_init()
4470 (amdgpu_ip_version(adev, GC_HWIP, 0) > in amdgpu_device_init()
[all …]
H A Damdgpu_ucode.c1325 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in amdgpu_ucode_legacy_naming()
1338 } else if (block_type == GC_HWIP) { in amdgpu_ucode_legacy_naming()
1339 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_ucode_legacy_naming()
1401 case GC_HWIP: in amdgpu_ucode_ip_version_decode()
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_int_process_v9.c170 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { in event_interrupt_poison_consumption_v9()
177 } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { in event_interrupt_poison_consumption_v9()

123