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Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 48) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_irq.c695 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()
726 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()
783 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_outbox_irq_state()
809 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_trace_irq_state()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_ai.c246 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()
304 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
H A Damdgpu_irq.h43 AMDGPU_IRQ_STATE_ENABLE, enumerator
H A Dmxgpu_nv.c288 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()
352 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
H A Dmxgpu_vi.c507 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()
540 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
H A Dnbio_v7_4.c464 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()
509 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
H A Dsi_dma.c590 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
606 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
H A Dgfx_v9_4_3.c3059 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3106 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_reg_fault_state()
3110 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_reg_fault_state()
3120 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_priv_reg_fault_state()
3146 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_bad_op_fault_state()
3150 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_bad_op_fault_state()
3160 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_bad_op_fault_state()
3185 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_inst_fault_state()
3189 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_inst_fault_state()
H A Dnbif_v6_3_1.c491 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbif_v6_3_1_set_ras_err_event_athub_irq_state()
H A Dvce_v2_0.c555 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
H A Dvpe_v6_1.c323 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in vpe_v6_1_set_trap_irq_state()
H A Damdgpu_irq.c538 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
H A Dsdma_v2_4.c999 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1015 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
H A Dgfx_v12_0.c4654 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_gfx_eop_interrupt_state()
4705 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_compute_eop_interrupt_state()
4813 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_reg_fault_state()
4822 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()
4836 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()
4859 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_bad_op_fault_state()
4868 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()
4882 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()
4904 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_inst_fault_state()
4913 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_inst_fault_state()
H A Dcik_sdma.c1110 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1126 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
H A Dgfx_v9_0.c5958 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
5961 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()
6010 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
6056 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()
6059 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
6069 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
6092 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_bad_op_fault_state()
6095 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_bad_op_fault_state()
6125 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()
6128 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
[all …]
H A Dnbio_v4_3.c573 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbio_v4_3_set_ras_err_event_athub_irq_state()
H A Dsdma_v3_0.c1337 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
1353 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
H A Dgfx_v11_0.c6195 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()
6252 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_compute_eop_interrupt_state()
6360 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_reg_fault_state()
6369 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6383 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6406 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_bad_op_fault_state()
6415 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6429 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6451 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_inst_fault_state()
6460 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
H A Dgmc_v12_0.c70 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v12_0_vm_fault_interrupt_state()
H A Dgmc_v11_0.c80 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v11_0_vm_fault_interrupt_state()
H A Dgfx_v6_0.c3215 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3244 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3278 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()
3303 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
H A Dgmc_v10_0.c80 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
H A Dgmc_v6_0.c1054 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
H A Dvce_v3_0.c733 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()

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