| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.h | 85 Register PredReg; in getVPTInstrPredicate() local
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| H A D | Thumb2InstrInfo.cpp | 73 Register PredReg; in ReplaceTailWithBranchTo() local
121 Register PredReg; in isLegalToSplitMBBAt() local
291 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate()
551 Register PredReg; in rewriteT2FrameIndex() local
767 Register &PredReg) { in getITInstrPredicate()
788 Register &PredReg) { in getVPTInstrPredicate()
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| H A D | MVEVPTBlockPass.cpp | 106 Register PredReg; in StepOverPredicatedInstrs() local
251 Register PredReg; in InsertVPTBlocks() local
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| H A D | ARMLoadStoreOptimizer.cpp | 490 unsigned PredReg) { in UpdateBaseRegUses()
907 Register PredReg; in MergeOpsUpdate() local
1296 Register PredReg; in MergeBaseUpdateLSMultiple() local
1492 Register PredReg; in MergeBaseUpdateLoadStore() local
1630 Register PredReg; in MergeBaseUpdateLSDouble() local
1800 Register PredReg; in FixInvalidRegPairOp() local
1900 Register PredReg; in LoadStoreMultipleOpti() local
2259 Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) { in CanFormLdStDWord()
2421 Register BaseReg, PredReg; in RescheduleOps() local
2522 Register PredReg; in RescheduleLoadStoreInstrs() local
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| H A D | Thumb2SizeReduction.cpp | 472 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
690 Register PredReg; in ReduceSpecial() local
732 Register PredReg; in ReduceSpecial() local
803 Register PredReg; in ReduceTo2Addr() local
896 Register PredReg; in ReduceToNarrow() local
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| H A D | ThumbRegisterInfo.cpp | 65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| H A D | Thumb2ITBlockPass.cpp | 202 Register PredReg; in InsertITInstructions() local
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| H A D | ARMBaseRegisterInfo.cpp | 499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
852 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| H A D | MLxExpansionPass.cpp | 282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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| H A D | ARMConstantIslandPass.cpp | 1456 Register PredReg; in createNewWater() local
1502 Register PredReg; in createNewWater() local
1526 Register PredReg; in createNewWater() local
1929 Register PredReg; in optimizeThumb2Branches() local
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| H A D | ARMFrameLowering.cpp | 511 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
525 unsigned PredReg = 0) { in emitSPUpdate()
2818 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr() local
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| H A D | ARMISelDAGToDAG.cpp | 1745 SDValue PredReg; in tryMVEIndexedLoad() local
2916 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in SelectCDE_CXxD() local
4270 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4293 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4315 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
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| H A D | ARMBaseInstrInfo.cpp | 2243 Register &PredReg) { in getInstrPredicate()
2273 Register PredReg; in commuteInstructionImpl() local
2481 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate()
5594 Register PredReg; in findCMPToFoldIntoCBZ() local
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| H A D | ARMExpandPseudoInsts.cpp | 975 Register PredReg; in ExpandMOV32BitImm() local
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| H A D | HexagonMCCompound.cpp | 177 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
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| H A D | HexagonMCChecker.cpp | 68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg()
94 unsigned PredReg = Hexagon::NoRegister; in init() local
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 321 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred()
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| H A D | HexagonInstrInfo.cpp | 1693 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
4513 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg()
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| H A D | HexagonHardwareLoops.cpp | 648 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1293 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr()
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